More VexRiscv smp cluster probes
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@ -8,7 +8,7 @@ import spinal.lib.bus.bmb.sim.BmbMemoryAgent
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import spinal.lib.bus.bmb.{Bmb, BmbArbiter, BmbDecoder, BmbExclusiveMonitor, BmbInvalidateMonitor, BmbParameter}
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import spinal.lib.com.jtag.Jtag
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import spinal.lib.com.jtag.sim.JtagTcp
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import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCacheConfig}
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import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
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import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
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import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
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@ -491,10 +491,21 @@ object VexRiscvSmpClusterOpenSbi extends App{
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simConfig.allOptimisation
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simConfig.addSimulatorFlag("--threads 1")
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val cpuCount = 4
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val cpuCount = 1
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val withStall = false
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simConfig.workspaceName("rawr_4c").compile(VexRiscvSmpClusterGen.vexRiscvCluster(cpuCount, resetVector = 0x80000000l)).doSimUntilVoid(seed = 42){dut =>
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def gen = {
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val dut = VexRiscvSmpClusterGen.vexRiscvCluster(cpuCount, resetVector = 0x80000000l)
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dut.cpus.foreach{cpu =>
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cpu.core.children.foreach{
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case cache : InstructionCache => cache.io.cpu.decode.simPublic()
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case _ =>
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}
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}
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dut
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}
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simConfig.workspaceName("rawr_4c").compile(gen).doSimUntilVoid(seed = 42){dut =>
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// dut.clockDomain.forkSimSpeedPrinter(1.0)
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VexRiscvSmpClusterTestInfrastructure.init(dut)
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val ram = VexRiscvSmpClusterTestInfrastructure.ram(dut, withStall)
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@ -511,17 +522,39 @@ object VexRiscvSmpClusterOpenSbi extends App{
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ram.memory.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio")
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import spinal.core.sim._
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var iMemReadBytes, dMemReadBytes, dMemWriteBytes = 0l
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var iMemReadBytes, dMemReadBytes, dMemWriteBytes, iMemSequencial,iMemRequests = 0l
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var reportTimer = 0
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var reportCycle = 0
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import java.io._
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val csv = new PrintWriter(new File("bench.csv" ))
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csv.write(s"reportCycle,iMemReadBytes,dMemReadBytes,dMemWriteBytes\n")
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val iMemCtx = Array.tabulate(cpuCount)(i => new {
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var sequencialPrediction = 0l
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val cache = dut.cpus(i).core.children.find(_.isInstanceOf[InstructionCache]).head.asInstanceOf[InstructionCache].io.cpu.decode
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})
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csv.write(s"reportCycle,iMemReadBytes,dMemReadBytes,dMemWriteBytes,miaou,asd\n")
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dut.clockDomain.onSamplings{
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dut.io.iMems.foreach{ iMem =>
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if(iMem.cmd.valid.toBoolean && iMem.cmd.ready.toBoolean){
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iMemReadBytes += iMem.cmd.length.toInt+1
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for(i <- 0 until cpuCount; iMem = dut.io.iMems(i); ctx = iMemCtx(i)){
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// if(iMem.cmd.valid.toBoolean && iMem.cmd.ready.toBoolean){
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// val length = iMem.cmd.length.toInt + 1
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// val address = iMem.cmd.address.toLong
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// iMemReadBytes += length
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// iMemRequests += 1
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// }
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if(ctx.cache.isValid.toBoolean && !ctx.cache.mmuRefilling.toBoolean && !ctx.cache.mmuException.toBoolean){
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val address = ctx.cache.physicalAddress.toLong
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val length = ctx.cache.p.bytePerLine.toLong
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val mask = ~(length-1)
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if(ctx.cache.cacheMiss.toBoolean) {
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iMemReadBytes += length
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iMemRequests += 1
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if ((address & mask) == (ctx.sequencialPrediction & mask)) {
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iMemSequencial += 1
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}
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}
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if(!ctx.cache.isStuck.toBoolean) {
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ctx.sequencialPrediction = address + length
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}
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}
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}
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if(dut.io.dMem.cmd.valid.toBoolean && dut.io.dMem.cmd.ready.toBoolean){
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@ -533,12 +566,18 @@ object VexRiscvSmpClusterOpenSbi extends App{
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}
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reportTimer = reportTimer + 1
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reportCycle = reportCycle + 1
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if(reportTimer == 100000){
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if(reportTimer == 400000){
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reportTimer = 0
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// println(f"\n** c=${reportCycle} ir=${iMemReadBytes*1e-6}%5.2f dr=${dMemReadBytes*1e-6}%5.2f dw=${dMemWriteBytes*1e-6}%5.2f **\n")
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csv.write(s"$reportCycle,$iMemReadBytes,$dMemReadBytes,$dMemWriteBytes\n")
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csv.write(s"$reportCycle,$iMemReadBytes,$dMemReadBytes,$dMemWriteBytes,$iMemRequests,$iMemSequencial\n")
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csv.flush()
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reportCycle = 0
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iMemReadBytes = 0
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dMemReadBytes = 0
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dMemWriteBytes = 0
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iMemRequests = 0
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iMemSequencial = 0
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}
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}
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