Fix muldiv plugin for CPU configs without memory/writeback stages
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@ -78,13 +78,19 @@ class MulDivIterativePlugin(genMul : Boolean = true,
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val rs2 = Reg(UInt(32 bits))
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val accumulator = Reg(UInt(65 bits))
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//FrontendOK is only used for CPU configs without memory/writeback stages, were it is required to wait one extra cycle
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// to let's the frontend process rs1 rs2 registers
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val frontendOk = if(flushStage != execute) True else RegInit(False) setWhen(arbitration.isValid && ((if(genDiv) input(IS_DIV) else False) || (if(genMul) input(IS_MUL) else False))) clearWhen(arbitration.isMoving)
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val mul = ifGen(genMul) (if(customMul != null) customMul(rs1,rs2,memory,pipeline) else new Area{
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assert(isPow2(mulUnrollFactor))
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val counter = Counter(32 / mulUnrollFactor + 1)
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val done = counter.willOverflowIfInc
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when(arbitration.isValid && input(IS_MUL)){
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when(!done){
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when(!frontendOk || !done){
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arbitration.haltItself := True
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}
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when(frontendOk && !done){
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arbitration.haltItself := True
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counter.increment()
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rs2 := rs2 |>> mulUnrollFactor
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@ -113,8 +119,10 @@ class MulDivIterativePlugin(genMul : Boolean = true,
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val done = Reg(Bool) setWhen(counter === counter.end-1) clearWhen(!arbitration.isStuck)
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val result = Reg(Bits(32 bits))
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when(arbitration.isValid && input(IS_DIV)){
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when(!done){
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when(!frontendOk || !done){
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arbitration.haltItself := True
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}
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when(frontendOk && !done){
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counter.increment()
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def stages(inNumerator: UInt, inRemainder: UInt, stage: Int): Unit = stage match {
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@ -140,16 +148,11 @@ class MulDivIterativePlugin(genMul : Boolean = true,
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}
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output(REGFILE_WRITE_DATA) := result
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// when(input(INSTRUCTION)(13 downto 12) === "00" && counter === 0 && rs2 =/= 0 && rs1 < 16 && rs2 < 16 && !input(RS1).msb && !input(RS2).msb) {
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// output(REGFILE_WRITE_DATA) := B(rs1(3 downto 0) / rs2(3 downto 0)).resized
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// counter.willIncrement := False
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// arbitration.haltItself := False
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// }
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}
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})
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//Execute stage logic to drive memory stage's input regs
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when(!arbitration.isStuck){
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when(if(flushStage != execute) !arbitration.isStuck else !frontendOk){
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accumulator := 0
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def twoComplement(that : Bits, enable: Bool): UInt = (Mux(enable, ~that, that).asUInt + enable.asUInt)
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val rs2NeedRevert = execute.input(RS2).msb && execute.input(IS_RS2_SIGNED)
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