Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

DBusCachedPlugin increase pendingMax to 64 to hide memory latency when saving a full context

This commit is contained in:
Dolu1990 2020-11-16 12:38:29 +01:00
parent ba523c627a
commit 832218dbec
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/vexriscv/ip/DataCache.scala
View File

@ -27,7 +27,7 @@ case class DataCacheConfig(cacheSize : Int,
withAmo : Boolean = false,
withExclusive : Boolean = false,
withInvalidate : Boolean = false,
pendingMax : Int = 32,
pendingMax : Int = 64,
directTlbHit : Boolean = false,
mergeExecuteMemory : Boolean = false,
asyncTagMemory : Boolean = false,