Add CSR
This commit is contained in:
Charles Papon
parent
f8678698fc
commit
835dd4ad50
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@ -65,6 +65,7 @@ class Briey(config: BrieyConfig) extends Component{
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val uart = master(Uart())
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val vga = master(Vga(vgaRgbConfig))
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val timerExternal = in(PinsecTimerCtrlExternal())
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val coreInterrupt = in Bool
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}
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val resetCtrlClockDomain = ClockDomain(
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@ -121,107 +122,6 @@ class Briey(config: BrieyConfig) extends Component{
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)
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val axi = new ClockingArea(axiClockDomain) {
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val core = new ClockingArea(coreClockDomain){
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val configLight = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, false),
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// new IBusSimplePlugin(
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// interfaceKeepData = false,
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// catchAccessFault = false
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// ),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = false,
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catchAccessFault = false,
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catchMemoryTranslationMiss = false,
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asyncTagMemory = false,
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twoStageLogic = true
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)
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// askMemoryTranslation = true,
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 4
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// )
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),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = false,
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// catchAccessFault = false
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = false,
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catchIllegal = false,
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catchUnaligned = false,
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catchMemoryTranslationMiss = false
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),
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memoryTranslatorPortConfig = null
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 6
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// )
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),
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new StaticMemoryTranslatorPlugin(
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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bypassWriteBackBuffer = false,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new DebugPlugin(axiClockDomain),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = NONE
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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val cpu = new VexRiscv(configLight)
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var iBus : Axi4Bus = null
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var dBus : Axi4Bus = null
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var debugBus : Apb3 = null
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for(plugin <- configLight.plugins) plugin match{
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case plugin : IBusSimplePlugin => iBus = plugin.iBus.toAxi4ReadOnly()
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case plugin : IBusCachedPlugin => iBus = plugin.iBus.toAxi4ReadOnly()
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case plugin : DBusSimplePlugin => dBus = plugin.dBus.toAxi4Shared()
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case plugin : DBusCachedPlugin => dBus = plugin.dBus.toAxi4Shared(true)
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case plugin : DebugPlugin => {
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resetCtrl.coreResetUnbuffered setWhen(plugin.io.resetOut)
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debugBus = plugin.io.bus.toApb3()
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}
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case _ =>
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}
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}
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val ram = Axi4SharedOnChipRam(
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dataWidth = 32,
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byteCount = onChipRamSize,
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@ -282,6 +182,136 @@ class Briey(config: BrieyConfig) extends Component{
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)
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val vgaCtrl = Axi4VgaCtrl(vgaCtrlConfig)
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val core = new ClockingArea(coreClockDomain){
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val configLight = VexRiscvConfig(
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plugins = List(
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new PcManagerSimplePlugin(0x00000000l, false),
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// new IBusSimplePlugin(
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// interfaceKeepData = false,
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// catchAccessFault = false
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// ),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = false,
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catchAccessFault = false,
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catchMemoryTranslationMiss = false,
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asyncTagMemory = false,
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twoStageLogic = true
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)
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// askMemoryTranslation = true,
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 4
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// )
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),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = false,
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// catchAccessFault = false
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = false,
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catchIllegal = false,
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catchUnaligned = false,
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catchMemoryTranslationMiss = false
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),
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memoryTranslatorPortConfig = null
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 6
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// )
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),
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new StaticMemoryTranslatorPlugin(
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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),
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new LightShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new DebugPlugin(axiClockDomain),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = false,
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prediction = STATIC
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),
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new CsrPlugin(
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config = MachineCsrConfig(
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catchIllegalAccess = false,
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mvendorid = null,
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marchid = null,
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mimpid = null,
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mhartid = null,
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misaExtensionsInit = 66,
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misaAccess = CsrAccess.NONE,
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mtvecAccess = CsrAccess.NONE,
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mtvecInit = 0x00000020l,
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mepcAccess = CsrAccess.READ_WRITE,
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mscratchGen = false,
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mcauseAccess = CsrAccess.READ_ONLY,
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mbadaddrAccess = CsrAccess.READ_ONLY,
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mcycleAccess = CsrAccess.NONE,
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minstretAccess = CsrAccess.NONE,
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ecallGen = false,
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wfiGen = false,
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ucycleAccess = CsrAccess.NONE
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)
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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val cpu = new VexRiscv(configLight)
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var iBus : Axi4ReadOnly = null
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var dBus : Axi4Shared = null
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var debugBus : Apb3 = null
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for(plugin <- configLight.plugins) plugin match{
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case plugin : IBusSimplePlugin => iBus = plugin.iBus.toAxi4ReadOnly()
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case plugin : IBusCachedPlugin => iBus = plugin.iBus.toAxi4ReadOnly()
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case plugin : DBusSimplePlugin => dBus = plugin.dBus.toAxi4Shared()
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case plugin : DBusCachedPlugin => dBus = plugin.dBus.toAxi4Shared(true)
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case plugin : CsrPlugin => {
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plugin.externalInterrupt := BufferCC(io.coreInterrupt)
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plugin.timerInterrupt := timerCtrl.io.interrupt
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}
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case plugin : DebugPlugin => {
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resetCtrl.coreResetUnbuffered setWhen(plugin.io.resetOut)
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debugBus = plugin.io.bus.toApb3()
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}
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case _ =>
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}
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}
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val axiCrossbar = Axi4CrossbarFactory()
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axiCrossbar.addSlaves(
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@ -324,6 +354,12 @@ class Briey(config: BrieyConfig) extends Component{
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ctrl.readRsp << crossbar.readRsp
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})
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axiCrossbar.addPipelining(core.dBus)((cpu,crossbar) => {
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cpu.sharedCmd >> crossbar.sharedCmd
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cpu.writeData >> crossbar.writeData
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cpu.writeRsp << crossbar.writeRsp
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cpu.readRsp <-< crossbar.readRsp
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})
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axiCrossbar.build()
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