add icache flush test

src/test/cpp/raw/icache/.gitignore

@@ -0,0 +1,4 @@
+*.map
+*.v
+*.elf
+*.o

src/test/cpp/raw/icache/build/icache.asm

@@ -0,0 +1,53 @@
+
+build/icache.elf:     file format elf32-littleriscv
+
+
+Disassembly of section .crt_section:
+
+80000000 <_start>:
+80000000:	00000097          	auipc	ra,0x0
+80000004:	05408093          	addi	ra,ra,84 # 80000054 <fail>
+80000008:	30509073          	csrw	mtvec,ra
+
+8000000c <test1>:
+8000000c:	00100e13          	li	t3,1
+80000010:	00100093          	li	ra,1
+80000014:	00300113          	li	sp,3
+80000018:	00208093          	addi	ra,ra,2
+8000001c:	02209c63          	bne	ra,sp,80000054 <fail>
+
+80000020 <test2>:
+80000020:	00100e13          	li	t3,1
+80000024:	01300093          	li	ra,19
+80000028:	00000117          	auipc	sp,0x0
+8000002c:	02410113          	addi	sp,sp,36 # 8000004c <test2_trigger>
+80000030:	0100006f          	j	80000040 <test2_aligned>
+80000034:	00000013          	nop
+80000038:	00000013          	nop
+8000003c:	00000013          	nop
+
+80000040 <test2_aligned>:
+80000040:	00112023          	sw	ra,0(sp)
+80000044:	0000100f          	fence.i
+80000048:	0040006f          	j	8000004c <test2_trigger>
+
+8000004c <test2_trigger>:
+8000004c:	0080006f          	j	80000054 <fail>
+80000050:	0100006f          	j	80000060 <pass>
+
+80000054 <fail>:
+80000054:	f0100137          	lui	sp,0xf0100
+80000058:	f2410113          	addi	sp,sp,-220 # f00fff24 <pass+0x700ffec4>
+8000005c:	01c12023          	sw	t3,0(sp)
+
+80000060 <pass>:
+80000060:	f0100137          	lui	sp,0xf0100
+80000064:	f2010113          	addi	sp,sp,-224 # f00fff20 <pass+0x700ffec0>
+80000068:	00012023          	sw	zero,0(sp)
+8000006c:	00000013          	nop
+80000070:	00000013          	nop
+80000074:	00000013          	nop
+80000078:	00000013          	nop
+8000007c:	00000013          	nop
+80000080:	00000013          	nop
+	...

src/test/cpp/raw/icache/build/icache.hex

@@ -0,0 +1,11 @@
+:0200000480007A
+:10000000970000009380400573905030130E10004D
+:10001000930010001301300093802000639C2002A5
+:10002000130E10009300300117010000130141026C
+:100030006F00000113000000130000001300000017
+:10004000232011000F1000006F0040006F0080009F
+:100050006F000001370110F0130141F22320C101AC
+:10006000370110F0130101F22320010013000000FA
+:100070001300000013000000130000001300000034
+:10008000130000000000000000000000000000005D
+:00000001FF

src/test/cpp/raw/icache/makefile

@@ -0,0 +1,3 @@
+PROJ_NAME=icache
+
+include ../common/asm.mk

src/test/cpp/raw/icache/src/crt.S

@@ -0,0 +1,44 @@
+.globl _star
+#define TEST_ID x28
+
+_start:
+    la x1, fail
+    csrw mtvec, x1
+
+test1: //Dummy test
+    li TEST_ID, 1
+    li x1, 1
+    li x2, 3
+    addi x1, x1, 2
+    bne x1, x2, fail
+
+test2:
+    li TEST_ID, 1
+    li x1, 0x13 //nop
+    la x2, test2_trigger
+    j test2_aligned
+.align(4)
+test2_aligned:
+    sw x1, 0(x2)
+    fence.i
+    j test2_trigger
+test2_trigger:
+    j fail
+
+
+    j pass
+
+fail:
+    li x2, 0xF00FFF24
+    sw TEST_ID, 0(x2)
+
+pass:
+    li x2, 0xF00FFF20
+    sw x0, 0(x2)
+
+    nop
+    nop
+    nop
+    nop
+    nop
+    nop

src/test/cpp/raw/icache/src/ld

@@ -0,0 +1,16 @@
+OUTPUT_ARCH( "riscv" )
+
+MEMORY {
+  onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K
+}
+
+SECTIONS
+{
+
+   .crt_section :
+   {
+    . = ALIGN(4);
+    *crt.o(.text)
+   } > onChipRam
+
+}

src/test/cpp/regression/main.cpp

@@ -3559,6 +3559,10 @@ int main(int argc, char **argv, char **env) {
 //				redo(REDO,TestX28("mmu",mmuRef, sizeof(mmuRef)/4).noInstructionReadCheck()->run(4e4);)
 //			#endif
 
+            #ifdef IBUS_CACHED
+                redo(REDO,WorkspaceRegression("icache").withRiscvRef()->loadHex("../raw/icache/build/icache.hex")->bootAt(0x80000000u)->run(50e3););
+            #endif
+
             #ifdef MMU
                 redo(REDO,WorkspaceRegression("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
             #endif