add icache flush test
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parent
60a41bfc75
commit
8459d423b8
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*.map
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*.v
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*.elf
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*.o
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build/icache.elf: file format elf32-littleriscv
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Disassembly of section .crt_section:
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80000000 <_start>:
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80000000: 00000097 auipc ra,0x0
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80000004: 05408093 addi ra,ra,84 # 80000054 <fail>
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80000008: 30509073 csrw mtvec,ra
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8000000c <test1>:
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8000000c: 00100e13 li t3,1
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80000010: 00100093 li ra,1
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80000014: 00300113 li sp,3
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80000018: 00208093 addi ra,ra,2
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8000001c: 02209c63 bne ra,sp,80000054 <fail>
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80000020 <test2>:
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80000020: 00100e13 li t3,1
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80000024: 01300093 li ra,19
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80000028: 00000117 auipc sp,0x0
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8000002c: 02410113 addi sp,sp,36 # 8000004c <test2_trigger>
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80000030: 0100006f j 80000040 <test2_aligned>
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80000034: 00000013 nop
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80000038: 00000013 nop
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8000003c: 00000013 nop
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80000040 <test2_aligned>:
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80000040: 00112023 sw ra,0(sp)
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80000044: 0000100f fence.i
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80000048: 0040006f j 8000004c <test2_trigger>
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8000004c <test2_trigger>:
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8000004c: 0080006f j 80000054 <fail>
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80000050: 0100006f j 80000060 <pass>
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80000054 <fail>:
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80000054: f0100137 lui sp,0xf0100
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80000058: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffec4>
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8000005c: 01c12023 sw t3,0(sp)
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80000060 <pass>:
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80000060: f0100137 lui sp,0xf0100
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80000064: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffec0>
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80000068: 00012023 sw zero,0(sp)
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8000006c: 00000013 nop
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80000070: 00000013 nop
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80000074: 00000013 nop
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80000078: 00000013 nop
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8000007c: 00000013 nop
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80000080: 00000013 nop
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...
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:0200000480007A
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:10000000970000009380400573905030130E10004D
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:10001000930010001301300093802000639C2002A5
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:10002000130E10009300300117010000130141026C
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:100030006F00000113000000130000001300000017
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:10004000232011000F1000006F0040006F0080009F
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:100050006F000001370110F0130141F22320C101AC
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:10006000370110F0130101F22320010013000000FA
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:100070001300000013000000130000001300000034
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:10008000130000000000000000000000000000005D
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:00000001FF
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PROJ_NAME=icache
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include ../common/asm.mk
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.globl _star
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#define TEST_ID x28
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_start:
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la x1, fail
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csrw mtvec, x1
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test1: //Dummy test
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li TEST_ID, 1
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li x1, 1
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li x2, 3
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addi x1, x1, 2
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bne x1, x2, fail
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test2:
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li TEST_ID, 1
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li x1, 0x13 //nop
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la x2, test2_trigger
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j test2_aligned
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.align(4)
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test2_aligned:
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sw x1, 0(x2)
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fence.i
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j test2_trigger
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test2_trigger:
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j fail
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j pass
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fail:
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li x2, 0xF00FFF24
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sw TEST_ID, 0(x2)
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pass:
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li x2, 0xF00FFF20
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sw x0, 0(x2)
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nop
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nop
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nop
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nop
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nop
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nop
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OUTPUT_ARCH( "riscv" )
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MEMORY {
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onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K
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}
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SECTIONS
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{
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.crt_section :
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{
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. = ALIGN(4);
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*crt.o(.text)
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} > onChipRam
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}
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@ -3559,6 +3559,10 @@ int main(int argc, char **argv, char **env) {
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// redo(REDO,TestX28("mmu",mmuRef, sizeof(mmuRef)/4).noInstructionReadCheck()->run(4e4);)
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// #endif
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#ifdef IBUS_CACHED
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redo(REDO,WorkspaceRegression("icache").withRiscvRef()->loadHex("../raw/icache/build/icache.hex")->bootAt(0x80000000u)->run(50e3););
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#endif
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#ifdef MMU
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redo(REDO,WorkspaceRegression("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
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#endif
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