Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

DebugPlugin.fromBscane2 added

This commit is contained in:
Charles Papon 2021-03-10 20:35:44 +01:00
parent 67d2f72a4b
commit 845cfcb966
1 changed files with 15 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/main/scala/vexriscv/plugin/DebugPlugin.scala
View File

@ -7,6 +7,7 @@ import vexriscv._
import vexriscv.ip._ import vexriscv.ip._
import spinal.core._ import spinal.core._
import spinal.lib._ import spinal.lib._
import spinal.lib.blackbox.xilinx.s7.BSCANE2
import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config} import spinal.lib.bus.amba3.apb.{Apb3, Apb3Config}
import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig} import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
import spinal.lib.bus.bmb.{Bmb, BmbAccessCapabilities, BmbAccessParameter, BmbParameter} import spinal.lib.bus.bmb.{Bmb, BmbAccessCapabilities, BmbAccessParameter, BmbParameter}
@ -149,6 +150,20 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
jtagBridge.io.ctrl jtagBridge.io.ctrl
} }
def fromBscane2(usedId : Int): Unit ={
val jtagConfig = SystemDebuggerConfig()
val bscane2 = BSCANE2(usedId)
val jtagClockDomain = ClockDomain(bscane2.TCK)
val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain)
jtagBridge.io.ctrl << bscane2.toJtagTapInstructionCtrl()
val debugger = new SystemDebugger(jtagConfig)
debugger.io.remote <> jtagBridge.io.remote
debugger.io.mem <> this.from(debugger.io.mem.c)
}
} }
case class DebugExtensionIo() extends Bundle with IMasterSlave{ case class DebugExtensionIo() extends Bundle with IMasterSlave{