Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage

This commit is contained in:
Dolu1990 2020-04-29 13:59:43 +02:00
parent 7b80e1fc30
commit 86e0cbc1f3
2 changed files with 9 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/vexriscv/ip/InstructionCache.scala
View File

@ -22,6 +22,7 @@ case class InstructionCacheConfig( cacheSize : Int,
asyncTagMemory : Boolean,
twoCycleCache : Boolean = true,
twoCycleRam : Boolean = false,
twoCycleRamInnerMux : Boolean = false,
preResetFlush : Boolean = false,
bypassGen : Boolean = false ){
@ -404,7 +405,8 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
}else {
way.tags.readSync(io.cpu.prefetch.pc(lineRange), !io.cpu.fetch.isStuck)
}
val data = way.datas.readSync(io.cpu.prefetch.pc(lineRange.high downto memWordRange.low), !io.cpu.fetch.isStuck)
val dataMem = way.datas.readSync(io.cpu.prefetch.pc(lineRange.high downto memWordRange.low), !io.cpu.fetch.isStuck)
val data = if(!twoCycleRamInnerMux) dataMem.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange)) else dataMem
}
}
@ -415,7 +417,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
val id = OHToUInt(hits)
val error = read.waysValues.map(_.tag.error).read(id)
val data = read.waysValues.map(_.data).read(id)
val word = if(cpuDataWidth == memDataWidth) CombInit(data) else data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))
val word = if(cpuDataWidth == memDataWidth || !twoCycleRamInnerMux) CombInit(data) else data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))
io.cpu.fetch.data := (if(p.bypassGen) (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | word) else word)
if(twoCycleCache){
io.cpu.decode.data := RegNextWhen(io.cpu.fetch.data,!io.cpu.decode.isStuck)
@ -423,7 +425,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
}
if(twoCycleRam && wayCount == 1){
val cacheData = if(cpuDataWidth == memDataWidth) CombInit(read.waysValues.head.data) else read.waysValues.head.data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))
val cacheData = if(cpuDataWidth == memDataWidth || !twoCycleRamInnerMux) CombInit(read.waysValues.head.data) else read.waysValues.head.data.subdivideIn(cpuDataWidth bits).read(io.cpu.fetch.pc(memWordToCpuWordRange))
io.cpu.fetch.data := (if(p.bypassGen) (io.cpu.fetch.dataBypassValid ? io.cpu.fetch.dataBypass | cacheData) else cacheData)
}
@ -459,7 +461,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
val id = OHToUInt(hits)
val error = tags(id).error
val data = fetchStage.read.waysValues.map(way => stage(way.data)).read(id)
val word = if(cpuDataWidth == memDataWidth) data else data.subdivideIn(cpuDataWidth bits).read(io.cpu.decode.pc(memWordToCpuWordRange))
val word = if(cpuDataWidth == memDataWidth || !twoCycleRamInnerMux) data else data.subdivideIn(cpuDataWidth bits).read(io.cpu.decode.pc(memWordToCpuWordRange))
if(p.bypassGen) when(stage(io.cpu.fetch.dataBypassValid)){
word := stage(io.cpu.fetch.dataBypass)
}

4
src/test/scala/vexriscv/TestIndividualFeatures.scala
View File

@ -354,6 +354,7 @@ class IBusDimension(rvcRate : Double) extends VexRiscvDimension("IBus") {
val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET))
val relaxedPcCalculation, twoCycleCache, injectorStage = r.nextBoolean()
val twoCycleRam = r.nextBoolean() && twoCycleCache
val twoCycleRamInnerMux = r.nextBoolean() && twoCycleRam
val memDataWidth = List(32,64,128)(r.nextInt(3))
val bytePerLine = Math.max(memDataWidth/8, List(8,16,32,64)(r.nextInt(4)))
var cacheSize = 0
@ -384,7 +385,8 @@ class IBusDimension(rvcRate : Double) extends VexRiscvDimension("IBus") {
catchAccessFault = catchAll,
asyncTagMemory = false,
twoCycleRam = twoCycleRam,
twoCycleCache = twoCycleCache
twoCycleCache = twoCycleCache,
twoCycleRamInnerMux = twoCycleRamInnerMux
)
)
if(tighlyCoupled) p.newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0))