rework fetcher
This commit is contained in:
Dolu1990
parent
56fd73fbbc
commit
86efb75f6a
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@ -18,7 +18,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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val compressedGen : Boolean,
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val cmdToRspStageCount : Int,
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val injectorReadyCutGen : Boolean,
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val relaxedPcCalculation : Boolean,
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val prediction : BranchPrediction,
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val historyRamSizeLog2 : Int,
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val injectorStage : Boolean) extends Plugin[VexRiscv] with JumpService with IBusFetcher{
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@ -111,39 +110,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
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}
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val fetchPc = if(relaxedPcCalculation) new PcFetch {
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//PC calculation without Jump
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val pcReg = Reg(UInt(32 bits)) init(if(resetVector != null) resetVector else externalResetVector) addAttribute(Verilator.public)
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val pcPlus4 = pcReg + 4
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if (keepPcPlus4) KeepAttribute(pcPlus4)
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when(preOutput.fire) {
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pcReg := pcPlus4
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}
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//Realign
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if(compressedGen){
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when(preOutput.fire){
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pcReg(1 downto 0) := 0
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}
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}
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preOutput.valid := RegNext(True) init (False) // && !jump.pcLoad.valid
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preOutput.payload := pcReg
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//application of the selected jump request
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if(predictionPcLoad != null) {
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when(predictionPcLoad.valid) {
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pcReg := predictionPcLoad.payload
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preOutput.valid := False
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}
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}
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when(jump.pcLoad.valid) {
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pcReg := jump.pcLoad.payload
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}
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} else new PcFetch{
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val fetchPc = new PcFetch{
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//PC calculation without Jump
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val pcReg = Reg(UInt(32 bits)) init(if(resetVector != null) resetVector else externalResetVector) addAttribute(Verilator.public)
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val inc = RegInit(False)
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@ -216,14 +183,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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})
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// val iBusCmd = new Area {
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// def input = fetchPc.output
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//
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// // ...
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//
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// val output = Stream(UInt(32 bits))
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// }
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case class FetchRsp() extends Bundle {
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val pc = UInt(32 bits)
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val rsp = IBusSimpleRsp()
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@ -232,22 +191,51 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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val iBusRsp = new Area {
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val input = Stream(UInt(32 bits))
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val inputPipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount)
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val inputPipelineHalt = Vec(False, cmdToRspStageCount-1)
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for(i <- 0 until cmdToRspStageCount) {
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// val doFlush = if(i == cmdToRspStageCount- 1 && ???) killLastStage else flush
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inputPipeline(i) << {i match {
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case 0 => input.m2sPipeWithFlush(flush, relaxedPcCalculation, collapsBubble = false)
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case _ => inputPipeline(i-1).haltWhen(inputPipelineHalt(i-1)).m2sPipeWithFlush(flush,collapsBubble = false)
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}}
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// val input = Stream(UInt(32 bits))
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// val inputPipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount)
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// val inputPipelineHalt = Vec(False, cmdToRspStageCount-1)
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// for(i <- 0 until cmdToRspStageCount) {
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// inputPipeline(i) << {i match {
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// case 0 => input.m2sPipeWithFlush(flush, false, collapsBubble = false)
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// case _ => inputPipeline(i-1).haltWhen(inputPipelineHalt(i-1)).m2sPipeWithFlush(flush,collapsBubble = false)
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// }}
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// }
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// val stages = Array.fill(cmdToRspStageCount)(Stream(UInt(32 bits)))
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val stages = Array.fill(cmdToRspStageCount + 1)(new Bundle {
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val input = Stream(UInt(32 bits))
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val output = Stream(UInt(32 bits))
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val halt = Bool
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val inputSample = Bool
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})
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stages(0).input << fetchPc.output
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stages(0).inputSample := True
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for(s <- stages) {
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s.halt := False
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s.output << s.input.haltWhen(s.halt)
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}
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for((s,sNext) <- (stages, stages.tail).zipped) {
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sNext.input << s.output.m2sPipeWithFlush(flush, s != stages.head, collapsBubble = false)
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}
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//
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// val pipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount + 1)
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// val halts = Vec(False, cmdToRspStageCount)
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// for(i <- 0 until cmdToRspStageCount + 1) {
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// pipeline(i) << {i match {
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// case 0 => pipeline(0) << fetchPc.output.haltWhen(halts(i))
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// case 1 => pipeline(1).m2sPipeWithFlush(flush, false, collapsBubble = false)
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// case _ => inputPipeline(i-1).haltWhen(inputPipelineHalt(i-1)).m2sPipeWithFlush(flush,collapsBubble = false)
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// }}
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// }
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// ...
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val readyForError = True
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val output = Stream(FetchRsp())
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incomingInstruction setWhen(inputPipeline.map(_.valid).orR)
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incomingInstruction setWhen(stages.tail.map(_.input.valid).reduce(_ || _))
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}
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val decompressor = ifGen(decodePcGen)(new Area{
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@ -326,10 +314,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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val valids = pcUpdatedGen(True, False :: List(execute, memory, writeBack).map(_.arbitration.isStuck), true)
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pcValids := Vec(valids.takeRight(4))
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} else new Area{
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val valids = pcUpdatedGen(True, iBusRsp.inputPipeline.map(!_.ready) ++ (if (injectorStage) List(!decodeInput.ready) else Nil) ++ List(execute, memory, writeBack).map(_.arbitration.isStuck), relaxedPcCalculation)
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if(relaxedPcCalculation && fetchPrediction != null) when(fetchPc.predictionPcLoad.valid){
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valids(0).getDrivingReg := False
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}
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val valids = pcUpdatedGen(True, iBusRsp.stages.tail.map(!_.input.ready) ++ (if (injectorStage) List(!decodeInput.ready) else Nil) ++ List(execute, memory, writeBack).map(_.arbitration.isStuck), false)
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pcValids := Vec(valids.takeRight(4))
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}
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@ -426,7 +411,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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}
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def stage1ToInjectorPipe[T <: Data](input : T): (T,T) ={
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val iBusRspContext = iBusRsp.inputPipeline.tail.foldLeft(input)((data,stream) => RegNextWhen(data, stream.ready))
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val iBusRspContext = iBusRsp.stages.drop(1).dropRight(1).foldLeft(input)((data,stage) => RegNextWhen(data, stage.output.ready))
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// val decompressorContext = ifGen(compressedGen)(new Area{
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// val lastContext = RegNextWhen(iBusRspContext, decompressor.input.fire)
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// val output = decompressor.bufferValid ? lastContext | iBusRspContext
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@ -450,8 +435,8 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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val historyCache = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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val historyWrite = historyCache.writePort
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val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.inputPipeline(0).ready)
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val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.inputPipeline(0).payload >> 2).resized
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val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready)
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val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(0).input.payload >> 2).resized
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case class DynamicContext() extends Bundle{
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val hazard = Bool
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@ -459,7 +444,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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}
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val fetchContext = DynamicContext()
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fetchContext.hazard := hazard
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fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush)
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fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || flush)
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object PREDICTION_CONTEXT extends Stageable(DynamicContext())
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decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._2
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@ -509,8 +494,8 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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val history = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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val historyWrite = history.writePort
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val line = history.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush)
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val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))) else True)
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val line = history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, iBusRsp.stages(0).output.ready || flush)
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val hit = line.source === (iBusRsp.stages(1).input.payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.stages(1).input.payload(1))) else True)
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//Avoid stoping instruction fetch in the middle patch
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if(compressedGen && cmdToRspStageCount == 1){
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@ -518,9 +503,10 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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}
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//Avoid write to read hazard
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val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.inputPipeline(0).ready)
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val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.inputPipeline(0).payload >> 2).resized
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fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.inputPipeline(0).fire //XXX && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))
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val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready)
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val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(1).input.payload >> 2).resized
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//TODO improve predictionPcLoad way of doing things
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fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.stages(1).output.fire //XXX && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))
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fetchPc.predictionPcLoad.payload := line.target
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case class PredictionResult() extends Bundle{
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@ -23,14 +23,14 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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keepPcPlus4 = keepPcPlus4,
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decodePcGen = compressedGen,
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compressedGen = compressedGen,
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cmdToRspStageCount = (if(config.twoCycleCache) 2 else 1),
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cmdToRspStageCount = (if(config.twoCycleCache) 2 else 1) + (if(relaxedPcCalculation) 1 else 0),
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injectorReadyCutGen = false,
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relaxedPcCalculation = relaxedPcCalculation,
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prediction = prediction,
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historyRamSizeLog2 = historyRamSizeLog2,
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injectorStage = !config.twoCycleCache || injectorStage){
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import config._
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var iBus : InstructionCacheMemBus = null
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var mmuBus : MemoryTranslatorBus = null
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var privilegeService : PrivilegeService = null
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@ -99,18 +99,20 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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iBus = master(new InstructionCacheMemBus(IBusCachedPlugin.this.config)).setName("iBus")
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iBus <> cache.io.mem
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iBus.cmd.address.allowOverride := cache.io.mem.cmd.address // - debugAddressOffset
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val stageOffset = if(relaxedPcCalculation) 1 else 0
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def stages = iBusRsp.stages.drop(stageOffset)
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//Connect prefetch cache side
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cache.io.cpu.prefetch.isValid := fetchPc.output.valid
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cache.io.cpu.prefetch.pc := fetchPc.output.payload
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iBusRsp.input << fetchPc.output.haltWhen(cache.io.cpu.prefetch.haltIt)
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cache.io.cpu.prefetch.isValid := stages(0).input.valid
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cache.io.cpu.prefetch.pc := stages(0).input.payload
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stages(0).halt setWhen(cache.io.cpu.prefetch.haltIt)
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cache.io.cpu.fetch.isRemoved := flush
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val iBusRspOutputHalt = False
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if (mmuBus != null) {
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cache.io.cpu.fetch.mmuBus <> mmuBus
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(if(twoCycleCache) iBusRsp.inputPipelineHalt(0) else iBusRspOutputHalt) setWhen(mmuBus.cmd.isValid && !mmuBus.rsp.hit && !mmuBus.rsp.miss)
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(if(twoCycleCache) stages(1).halt else iBusRspOutputHalt) setWhen(mmuBus.cmd.isValid && !mmuBus.rsp.hit && !mmuBus.rsp.miss)
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} else {
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cache.io.cpu.fetch.mmuBus.rsp.physicalAddress := cache.io.cpu.fetch.mmuBus.cmd.virtualAddress
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cache.io.cpu.fetch.mmuBus.rsp.allowExecute := True
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@ -123,15 +125,15 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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}
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//Connect fetch cache side
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cache.io.cpu.fetch.isValid := iBusRsp.inputPipeline(0).valid
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cache.io.cpu.fetch.isStuck := !iBusRsp.inputPipeline(0).ready
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cache.io.cpu.fetch.pc := iBusRsp.inputPipeline(0).payload
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cache.io.cpu.fetch.isValid := stages(1).input.valid
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cache.io.cpu.fetch.isStuck := !stages(1).input.ready
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cache.io.cpu.fetch.pc := stages(1).input.payload
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if(twoCycleCache){
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cache.io.cpu.decode.isValid := iBusRsp.inputPipeline(1).valid
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cache.io.cpu.decode.isStuck := !iBusRsp.inputPipeline(1).ready
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cache.io.cpu.decode.pc := iBusRsp.inputPipeline(1).payload
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cache.io.cpu.decode.isValid := stages(2).input.valid
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cache.io.cpu.decode.isStuck := !stages(2).input.ready
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cache.io.cpu.decode.pc := stages(2).input.payload
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cache.io.cpu.decode.isUser := (if (privilegeService != null) privilegeService.isUser(decode) else False)
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if((!twoCycleRam || wayCount == 1) && !compressedGen && !injectorStage){
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@ -145,7 +147,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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// val missHalt = cache.io.cpu.fetch.isValid && cache.io.cpu.fetch.cacheMiss
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val cacheRsp = if(twoCycleCache) cache.io.cpu.decode else cache.io.cpu.fetch
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val cacheRspArbitration = iBusRsp.inputPipeline(if(twoCycleCache) 1 else 0)
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val cacheRspArbitration = stages(if(twoCycleCache) 2 else 1)
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var issueDetected = False
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val redoFetch = False //RegNext(False) init(False)
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when(cacheRsp.isValid && cacheRsp.cacheMiss && !issueDetected){
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@ -174,49 +176,12 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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}
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}
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iBusRsp.output.arbitrationFrom(cacheRspArbitration.haltWhen(issueDetected || iBusRspOutputHalt))
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cacheRspArbitration.halt setWhen(issueDetected || iBusRspOutputHalt)
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iBusRsp.output.arbitrationFrom(cacheRspArbitration.output)
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iBusRsp.output.rsp.inst := cacheRsp.data
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iBusRsp.output.pc := cacheRspArbitration.payload
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iBusRsp.output.pc := cacheRspArbitration.output.payload
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// if (dataOnDecode) {
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// decode.insert(INSTRUCTION) := cache.io.cpu.decode.data
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// } else {
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// iBusRsp.outputBeforeStage.arbitrationFrom(iBusRsp.inputPipeline(0))
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// iBusRsp.outputBeforeStage.rsp.inst := cache.io.cpu.fetch.data
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// iBusRsp.outputBeforeStage.pc := iBusRsp.inputPipeline(0).payload
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// }
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//
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// cache.io.cpu.decode.pc := injector.inputBeforeHalt.pc
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//
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// val ownDecode = pipeline.plugins.filter(_.isInstanceOf[InstructionInjector]).foldLeft(True)(_ && !_.asInstanceOf[InstructionInjector].isInjecting(decode))
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// cache.io.cpu.decode.isValid := decode.arbitration.isValid && ownDecode
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// cache.io.cpu.decode.isStuck := !injector.inputBeforeHalt.ready
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// cache.io.cpu.decode.isUser := (if (privilegeService != null) privilegeService.isUser(decode) else False)
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// // cache.io.cpu.decode.pc := decode.input(PC)
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//
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// redoBranch.valid := decode.arbitration.isValid && ownDecode && cache.io.cpu.decode.cacheMiss && !cache.io.cpu.decode.mmuMiss && !cache.io.cpu.decode.illegalAccess
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// redoBranch.payload := decode.input(PC)
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// when(redoBranch.valid) {
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// decode.arbitration.redoIt := True
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// decode.arbitration.flushAll := True
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// }
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// val redo = RegInit(False) clearWhen(decode.arbitration.isValid) setWhen(redoBranch.valid)
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// when(redoBranch.valid || redo){
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// service(classOf[InterruptionInhibitor]).inhibateInterrupts()
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// }
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// if (catchSomething) {
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// val accessFault = if (catchAccessFault) cache.io.cpu.decode.error else False
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// val mmuMiss = if (catchMemoryTranslationMiss) cache.io.cpu.decode.mmuMiss else False
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// val illegalAccess = if (catchIllegalAccess) cache.io.cpu.decode.illegalAccess else False
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// decodeExceptionPort.valid := decode.arbitration.isValid && ownDecode && (accessFault || mmuMiss || illegalAccess)
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// decodeExceptionPort.code := mmuMiss ? U(14) | 1
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// decodeExceptionPort.badAddr := decode.input(PC)
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// }
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memory plug new Area {
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@ -159,9 +159,8 @@ class IBusSimplePlugin(resetVector : BigInt,
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keepPcPlus4 = keepPcPlus4,
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decodePcGen = compressedGen,
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compressedGen = compressedGen,
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cmdToRspStageCount = busLatencyMin,
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cmdToRspStageCount = busLatencyMin + (if(relaxedPcCalculation) 1 else 0),
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injectorReadyCutGen = false,
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relaxedPcCalculation = relaxedPcCalculation,
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prediction = prediction,
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historyRamSizeLog2 = historyRamSizeLog2,
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injectorStage = injectorStage){
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@ -187,36 +186,49 @@ class IBusSimplePlugin(resetVector : BigInt,
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pipeline plug new FetchArea(pipeline) {
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//Avoid sending to many iBus cmd
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val pendingCmd = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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val pendingCmdNext = pendingCmd + iBus.cmd.fire.asUInt - iBus.rsp.fire.asUInt
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pendingCmd := pendingCmdNext
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val cmd = if(relaxedBusCmdValid) new Area {
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assert(relaxedPcCalculation, "relaxedBusCmdValid can only be used with relaxedPcCalculation")
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def input = fetchPc.output
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def output = iBusRsp.input
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???
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/* def inputStage = iBusRsp.stages(0)
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val busFork = Stream(UInt(32 bits))
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val busForkedReg = RegInit(False)
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if(!relaxedPcCalculation) busForkedReg clearWhen(flush)
|
||||
busForkedReg setWhen(iBus.cmd.fire)
|
||||
busForkedReg clearWhen(inputStage.output.ready)
|
||||
if(relaxedPcCalculation) busForkedReg clearWhen(flush)
|
||||
val busForked = Bool
|
||||
busForked := (if(!relaxedPcCalculation) (busForkedReg && !flush) else (busForkedReg))
|
||||
|
||||
|
||||
busFork.valid := inputStage.input.valid && !busForkedReg
|
||||
busFork.payload := inputStage.input.payload
|
||||
|
||||
inputStage.halt setWhen()
|
||||
output.valid := (inputStage.input.valid && iBus.cmd.fire) || busForked
|
||||
output.payload := input.payload
|
||||
input.ready := output.fire
|
||||
|
||||
val fork = StreamForkVex(input, 2, flush)
|
||||
val busFork = fork(0)
|
||||
val pipFork = fork(1)
|
||||
output << pipFork
|
||||
|
||||
val okBus = pendingCmd =/= pendingMax
|
||||
iBus.cmd.valid := busFork.valid && okBus
|
||||
iBus.cmd.pc := busFork.payload(31 downto 2) @@ "00"
|
||||
busFork.ready := iBus.cmd.ready && okBus
|
||||
busFork.ready := iBus.cmd.ready && okBus*/
|
||||
} else new Area {
|
||||
def input = fetchPc.output
|
||||
def output = iBusRsp.input
|
||||
def stage = iBusRsp.stages(if(relaxedPcCalculation) 1 else 0)
|
||||
stage.halt setWhen(stage.input.valid && (!iBus.cmd.valid || !iBus.cmd.ready))
|
||||
|
||||
output << input.continueWhen(iBus.cmd.fire)
|
||||
|
||||
iBus.cmd.valid := input.valid && output.ready && pendingCmd =/= pendingMax
|
||||
iBus.cmd.pc := input.payload(31 downto 2) @@ "00"
|
||||
iBus.cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax
|
||||
iBus.cmd.pc := stage.input.payload(31 downto 2) @@ "00"
|
||||
}
|
||||
|
||||
|
||||
|
||||
val rsp = new Area {
|
||||
import iBusRsp._
|
||||
//Manage flush for iBus transactions in flight
|
||||
|
|
@ -226,20 +238,19 @@ class IBusSimplePlugin(resetVector : BigInt,
|
|||
discardCounter := (if(relaxedPcCalculation) pendingCmdNext else pendingCmd - iBus.rsp.fire.asUInt)
|
||||
}
|
||||
|
||||
|
||||
val rspBuffer = StreamFifoLowLatency(IBusSimpleRsp(), cmdToRspStageCount + (if(relaxedBusCmdValid) 1 else 0))
|
||||
val rspBuffer = StreamFifoLowLatency(IBusSimpleRsp(), cmdToRspStageCount - (if(relaxedPcCalculation) 0 else 0))
|
||||
rspBuffer.io.push << iBus.rsp.throwWhen(discardCounter =/= 0).toStream
|
||||
rspBuffer.io.flush := flush
|
||||
|
||||
val fetchRsp = FetchRsp()
|
||||
fetchRsp.pc := inputPipeline.last.payload
|
||||
fetchRsp.pc := stages.last.output.payload
|
||||
fetchRsp.rsp := rspBuffer.io.pop.payload
|
||||
fetchRsp.rsp.error.clearWhen(!rspBuffer.io.pop.valid) //Avoid interference with instruction injection from the debug plugin
|
||||
|
||||
|
||||
var issueDetected = False
|
||||
val join = StreamJoin(Seq(inputPipeline.last, rspBuffer.io.pop), fetchRsp)
|
||||
inputPipeline.last.ready setWhen(!inputPipeline.last.valid)
|
||||
val join = StreamJoin(Seq(stages.last.output, rspBuffer.io.pop), fetchRsp)
|
||||
stages.last.output.ready setWhen(!stages.last.output.valid)
|
||||
output << join.haltWhen(issueDetected)
|
||||
|
||||
if(catchAccessFault){
|
||||
|
|
|
|||
|
|
@ -522,8 +522,8 @@ class TestIndividualFeatures extends FunSuite {
|
|||
// val seed = -2412372746600605141l
|
||||
|
||||
|
||||
// val testId = Some(mutable.HashSet[Int](15))
|
||||
// val seed = -8861778219266506530l
|
||||
// val testId = Some(mutable.HashSet[Int](1,6,11,17,23,24))
|
||||
// val seed = -7309275932954927463l
|
||||
|
||||
|
||||
val rand = new Random(seed)
|
||||
|
|
|
|||
Loading…
Reference in New Issue