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VexRiscv
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Merge pull request #288 from betrusted-io/expand-satp 

Expand SATP register to 22 bits per spec
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Dolu1990 2022-12-20 16:05:13 +01:00 committed by GitHub
parent 51b69a1527 bf3521f86a
commit 8a6a926401
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 2 deletions
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6
src/main/scala/vexriscv/plugin/MmuPlugin.scala
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@ -94,7 +94,8 @@ class MmuPlugin(ioRange : UInt => Bool,
val satp = new Area {
val mode = RegInit(False)
val asid = Reg(Bits(9 bits))
val ppn = Reg(UInt(20 bits))
// Bottom 20 bits are used in implementation, but top 2 bits are still stored for OS use.
val ppn = Reg(UInt(22 bits))
}
for(offset <- List(CSR.MSTATUS, CSR.SSTATUS)) csrService.rw(offset, 19 -> status.mxr, 18 -> status.sum, 17 -> status.mprv)
@ -233,7 +234,8 @@ class MmuPlugin(ioRange : UInt => Bool,
}
is(State.L1_CMD){
dBusAccess.cmd.valid := True
dBusAccess.cmd.address := csr.satp.ppn @@ vpn(1) @@ U"00"
// RV spec allows for 34-bit phys address in Sv32 mode; we only implement 32 bits and ignore the top 2 bits of satp.
dBusAccess.cmd.address := csr.satp.ppn(19 downto 0) @@ vpn(1) @@ U"00"
when(dBusAccess.cmd.ready){
state := State.L1_RSP
}