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VexRiscv
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Merge pull request #141 from betrusted-io/dev-asid 

Dev asid
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Dolu1990 2020-10-04 15:20:02 +02:00 committed by GitHub
parent b7e7faebad 72f85ef6c0
commit 8bd1785233
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1 changed files with 2 additions and 1 deletions
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src/main/scala/vexriscv/plugin/MmuPlugin.scala
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@ -92,11 +92,12 @@ class MmuPlugin(ioRange : UInt => Bool,
} }
val satp = new Area { val satp = new Area {
val mode = RegInit(False) val mode = RegInit(False)
val asid = Reg(Bits(9 bits))
val ppn = Reg(UInt(20 bits)) val ppn = Reg(UInt(20 bits))
} }
for(offset <- List(CSR.MSTATUS, CSR.SSTATUS)) csrService.rw(offset, 19 -> status.mxr, 18 -> status.sum, 17 -> status.mprv) for(offset <- List(CSR.MSTATUS, CSR.SSTATUS)) csrService.rw(offset, 19 -> status.mxr, 18 -> status.sum, 17 -> status.mprv)
csrService.rw(CSR.SATP, 31 -> satp.mode, 0 -> satp.ppn) csrService.rw(CSR.SATP, 31 -> satp.mode, 22 -> satp.asid, 0 -> satp.ppn)
} }
val core = pipeline plug new Area { val core = pipeline plug new Area {