#60 Got the new data cache design passing all tests and running linux
This commit is contained in:
Charles Papon
parent
fd4da77084
commit
8be40e637b
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@ -33,6 +33,7 @@ case class ExceptionCause() extends Bundle{
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trait ExceptionService{
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def newExceptionPort(stage : Stage, priority : Int = 0) : Flow[ExceptionCause]
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def isExceptionPending() : Bool
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}
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trait PrivilegeService{
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@ -96,45 +96,45 @@ object LinuxGen {
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new DummyFencePlugin(), //TODO should be removed for design with caches
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//Uncomment the whole IBusSimplePlugin and comment IBusCachedPlugin if you want uncached iBus config
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new IBusSimplePlugin(
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resetVector = 0x80000000l,
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cmdForkOnSecondStage = false,
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cmdForkPersistence = false,
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prediction = NONE,
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historyRamSizeLog2 = 10,
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catchAccessFault = true,
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compressedGen = true,
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busLatencyMin = 1,
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injectorStage = true,
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memoryTranslatorPortConfig = withMmu generate MmuPortConfig(
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portTlbSize = 4
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)
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),
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//Uncomment the whole IBusCachedPlugin and comment IBusSimplePlugin if you want cached iBus config
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// new IBusCachedPlugin(
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// new IBusSimplePlugin(
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// resetVector = 0x80000000l,
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// compressedGen = true,
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// cmdForkOnSecondStage = false,
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// cmdForkPersistence = false,
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// prediction = NONE,
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// historyRamSizeLog2 = 10,
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// catchAccessFault = true,
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// compressedGen = true,
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// busLatencyMin = 1,
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// injectorStage = true,
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// config = InstructionCacheConfig(
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// cacheSize = 4096,
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// bytePerLine = 32,
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// wayCount = 1,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchIllegalAccess = true,
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// catchAccessFault = true,
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// asyncTagMemory = false,
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// twoCycleRam = false,
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// twoCycleCache = true
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// )
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// ),
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// memoryTranslatorPortConfig = MmuPortConfig(
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// memoryTranslatorPortConfig = withMmu generate MmuPortConfig(
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// portTlbSize = 4
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// )
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// ),
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//Uncomment the whole IBusCachedPlugin and comment IBusSimplePlugin if you want cached iBus config
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new IBusCachedPlugin(
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resetVector = 0x80000000l,
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compressedGen = true,
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prediction = NONE,
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injectorStage = true,
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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asyncTagMemory = false,
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twoCycleRam = false,
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twoCycleCache = true
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// )
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),
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memoryTranslatorPortConfig = MmuPortConfig(
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portTlbSize = 4
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)
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),
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// ).newTightlyCoupledPort(TightlyCoupledPortParameter("iBusTc", a => a(30 downto 28) === 0x0 && a(5))),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = true,
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@ -156,17 +156,16 @@ object LinuxGen {
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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atomicEntriesCount = 2
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)
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// ),
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// memoryTranslatorPortConfig = null
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// memoryTranslatorPortConfig = MmuPortConfig(
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// portTlbSize = 4
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atomicEntriesCount = 1
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// )
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),
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memoryTranslatorPortConfig = withMmu generate MmuPortConfig(
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portTlbSize = 4
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)
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),
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new StaticMemoryTranslatorPlugin(
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ioRange = _(31 downto 28) === 0xF
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),
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// new StaticMemoryTranslatorPlugin(
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// ioRange = _(31 downto 28) === 0xF
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// ),
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// new MemoryTranslatorPlugin(
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// tlbSize = 32,
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// virtualRange = _(31 downto 28) === 0xC,
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@ -238,12 +237,12 @@ object LinuxGen {
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new YamlPlugin("cpu0.yaml")
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)
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)
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// if(withMmu) config.plugins += new MmuPlugin(
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// virtualRange = a => True,
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// // virtualRange = x => x(31 downto 24) =/= 0x81, //TODO It fix the DTB kernel access (workaround)
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// ioRange = (x => if(litex) x(31 downto 28) === 0xB || x(31 downto 28) === 0xE || x(31 downto 28) === 0xF else x(31 downto 28) === 0xF),
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// allowUserIo = true
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// )
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if(withMmu) config.plugins += new MmuPlugin(
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virtualRange = a => True,
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// virtualRange = x => x(31 downto 24) =/= 0x81, //TODO It fix the DTB kernel access (workaround)
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ioRange = (x => if(litex) x(31 downto 28) === 0xB || x(31 downto 28) === 0xE || x(31 downto 28) === 0xF else x(31 downto 28) === 0xF),
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allowUserIo = true
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)
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config
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}
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@ -8,6 +8,8 @@ import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
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import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
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import spinal.lib.bus.simple._
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//TODO flush
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case class DataCacheConfig(cacheSize : Int,
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bytePerLine : Int,
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wayCount : Int,
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@ -71,13 +73,12 @@ object DataCacheCpuExecute{
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case class DataCacheCpuExecute(p : DataCacheConfig) extends Bundle with IMasterSlave{
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val isValid = Bool
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val isStuck = Bool
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val address = UInt(p.addressWidth bit)
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// val haltIt = Bool
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val args = DataCacheCpuExecuteArgs(p)
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override def asMaster(): Unit = {
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out(isValid, isStuck, args, address)
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out(isValid, args, address)
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// in(haltIt)
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}
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}
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@ -111,6 +112,7 @@ case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMaste
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val isStuck = Bool
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val isUser = Bool
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val haltIt = Bool
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val isWrite = Bool
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val data = Bits(p.cpuDataWidth bit)
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val address = UInt(p.addressWidth bit)
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val mmuException, unalignedAccess , accessError = Bool
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@ -120,7 +122,7 @@ case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMaste
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override def asMaster(): Unit = {
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out(isValid,isStuck,isUser, address)
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in(haltIt, data, mmuException, unalignedAccess, accessError)
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in(haltIt, data, mmuException, unalignedAccess, accessError, isWrite)
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outWithNull(clearAtomicEntries)
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}
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}
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@ -354,8 +356,8 @@ class DataCache(p : DataCacheConfig) extends Component{
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val data = Mem(Bits(wordWidth bit), wayWordCount)
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//Reads
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val tagsReadRsp = tags.readSync(tagsReadCmd.payload, tagsReadCmd.valid && !io.cpu.execute.isStuck)
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val dataReadRsp = data.readSync(dataReadCmd.payload, dataReadCmd.valid && !io.cpu.execute.isStuck)
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val tagsReadRsp = tags.readSync(tagsReadCmd.payload, tagsReadCmd.valid && !io.cpu.memory.isStuck)
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val dataReadRsp = data.readSync(dataReadCmd.payload, dataReadCmd.valid && !io.cpu.memory.isStuck)
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//Writes
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when(tagsWriteCmd.valid && tagsWriteCmd.way(i)){
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@ -380,7 +382,7 @@ class DataCache(p : DataCacheConfig) extends Component{
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dataWriteCmd.valid := False
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dataWriteCmd.payload.assignDontCare()
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when(io.cpu.execute.isValid && !io.cpu.execute.isStuck){
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when(io.cpu.execute.isValid && !io.cpu.memory.isStuck){
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tagsReadCmd.valid := True
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dataReadCmd.valid := True
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tagsReadCmd.payload := io.cpu.execute.address(lineRange)
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@ -460,7 +462,6 @@ class DataCache(p : DataCacheConfig) extends Component{
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val atomic = genAtomic generate new Area{
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case class AtomicEntry() extends Bundle{
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val valid = Bool()
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val size = UInt(2 bits)
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val address = UInt(addressWidth bits)
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def init: this.type ={
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@ -470,10 +471,9 @@ class DataCache(p : DataCacheConfig) extends Component{
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}
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val entries = Vec(Reg(AtomicEntry()).init, atomicEntriesCount)
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val entriesAllocCounter = Counter(atomicEntriesCount)
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val entriesHit = entries.map(e => e.valid && e.size === request.size && e.address === io.cpu.writeBack.address).orR
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val entriesHit = entries.map(e => e.valid && e.address === io.cpu.writeBack.address).orR
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when(io.cpu.writeBack.isValid && request.isAtomic && !request.wr){
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entries(entriesAllocCounter).valid := True
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entries(entriesAllocCounter).size := request.size //TODO remove size stuff
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entries(entriesAllocCounter).address := io.cpu.writeBack.address
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when(!io.cpu.writeBack.isStuck){
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entriesAllocCounter.increment()
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@ -486,11 +486,11 @@ class DataCache(p : DataCacheConfig) extends Component{
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val memCmdSent = RegInit(False) setWhen (io.mem.cmd.ready) clearWhen (!io.cpu.writeBack.isStuck)
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io.cpu.redo := mmuRsp.refilling
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io.cpu.redo := False
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io.cpu.writeBack.accessError := False
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io.cpu.writeBack.mmuException := io.cpu.writeBack.isValid && (if(catchIllegal) mmuRsp.exception || (!mmuRsp.allowWrite && request.wr) || (!mmuRsp.allowRead && !request.wr) || (!mmuRsp.allowUser && io.cpu.writeBack.isUser) else False)
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io.cpu.writeBack.unalignedAccess := io.cpu.writeBack.isValid && (if(catchUnaligned) ((request.size === 2 && mmuRsp.physicalAddress(1 downto 0) =/= 0) || (request.size === 1 && mmuRsp.physicalAddress(0 downto 0) =/= 0)) else False)
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io.cpu.writeBack.isWrite := request.wr
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when(io.cpu.writeBack.isValid) {
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when(request.forceUncachedAccess || mmuRsp.isIoAccess) {
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@ -503,6 +503,11 @@ class DataCache(p : DataCacheConfig) extends Component{
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io.mem.cmd.data := request.data
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io.mem.cmd.length := 0
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io.mem.cmd.last := True
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if(genAtomic) when(request.isAtomic && !atomic.entriesHit){
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io.mem.cmd.valid := False
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io.cpu.writeBack.haltIt := False
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}
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} otherwise {
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when(waysHit || request.wr) { //Do not require a cache refill ?
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//Data cache update
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@ -524,6 +529,12 @@ class DataCache(p : DataCacheConfig) extends Component{
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//On write to read colisions
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io.cpu.redo := !request.wr && (colisions & waysHits) =/= 0
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if(genAtomic) when(request.isAtomic && !atomic.entriesHit){
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io.mem.cmd.valid := False
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dataWriteCmd.valid := False
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io.cpu.writeBack.haltIt := False
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}
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} otherwise { //Do refill
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//Emit cmd
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@ -554,6 +565,7 @@ class DataCache(p : DataCacheConfig) extends Component{
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loaderValid := False
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io.cpu.writeBack.haltIt := False
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}
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io.cpu.redo setWhen(io.cpu.writeBack.isValid && mmuRsp.refilling)
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assert(!(io.cpu.writeBack.isValid && !io.cpu.writeBack.haltIt && io.cpu.writeBack.isStuck), "writeBack stuck by another plugin is not allowed")
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@ -561,9 +573,6 @@ class DataCache(p : DataCacheConfig) extends Component{
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when(request.isAtomic && request.wr){
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io.cpu.writeBack.data := (!atomic.entriesHit).asBits.resized
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}
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when(request.isAtomic && !atomic.entriesHit){
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io.mem.cmd.mask := 0
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}
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}
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}
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@ -285,6 +285,9 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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interface
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}
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var exceptionPending : Bool = null
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override def isExceptionPending(): Bool = exceptionPending
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var jumpInterface : Flow[UInt] = null
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var timerInterrupt, externalInterrupt, softwareInterrupt : Bool = null
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var externalInterruptS : Bool = null
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@ -378,7 +381,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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jumpInterface.valid := False
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jumpInterface.payload.assignDontCare()
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exceptionPending = False
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timerInterrupt = in Bool() setName("timerInterrupt")
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externalInterrupt = in Bool() setName("externalInterrupt")
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softwareInterrupt = in Bool() setName("softwareInterrupt")
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@ -677,7 +680,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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else
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exceptionValidsRegs(stageId) := False
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}
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if(stage != stages.last) when(stage.arbitration.isFlushed){
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when(stage.arbitration.isFlushed){
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exceptionValids(stageId) := False
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}
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}
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@ -688,6 +691,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
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//Avoid the PC register of the last stage to change durring an exception handleing (Used to fill Xepc)
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stages.last.dontSample.getOrElseUpdate(PC, ArrayBuffer[Bool]()) += exceptionValids.last
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exceptionPending setWhen(exceptionValidsRegs.orR)
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} else null
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@ -7,7 +7,7 @@ import spinal.lib._
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import spinal.lib.bus.amba4.axi.Axi4
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class DAxiCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : Any = null) extends DBusCachedPlugin(config, memoryTranslatorPortConfig){
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class DAxiCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : Any = null) extends DBusCachedPlugin(config, memoryTranslatorPortConfig) {
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var dAxi : Axi4 = null
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override def build(pipeline: VexRiscv): Unit = {
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@ -20,7 +20,7 @@ class DAxiCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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class DBusCachedPlugin(config : DataCacheConfig,
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memoryTranslatorPortConfig : Any = null,
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csrInfo : Boolean = false) extends Plugin[VexRiscv]{
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csrInfo : Boolean = false) extends Plugin[VexRiscv] with DBusAccessService {
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import config._
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var dBus : DataCacheMemBus = null
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var mmuBus : MemoryTranslatorBus = null
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@ -28,11 +28,19 @@ class DBusCachedPlugin(config : DataCacheConfig,
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var privilegeService : PrivilegeService = null
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var redoBranch : Flow[UInt] = null
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@dontName var dBusAccess : DBusAccess = null
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override def newDBusAccess(): DBusAccess = {
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assert(dBusAccess == null)
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dBusAccess = DBusAccess()
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dBusAccess
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}
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object MEMORY_ENABLE extends Stageable(Bool)
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object MEMORY_MANAGMENT extends Stageable(Bool)
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object MEMORY_WR extends Stageable(Bool)
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object MEMORY_ADDRESS_LOW extends Stageable(UInt(2 bits))
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object MEMORY_ATOMIC extends Stageable(Bool)
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object IS_DBUS_SHARING extends Stageable(Bool())
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override def setup(pipeline: VexRiscv): Unit = {
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import Riscv._
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@ -44,8 +52,9 @@ class DBusCachedPlugin(config : DataCacheConfig,
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SRC1_CTRL -> Src1CtrlEnum.RS,
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SRC_USE_SUB_LESS -> False,
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MEMORY_ENABLE -> True,
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RS1_USE -> True
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) ++ (if (catchSomething) List(IntAluPlugin.ALU_CTRL -> IntAluPlugin.AluCtrlEnum.ADD_SUB) else Nil) //Used for access fault bad address in memory stage
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RS1_USE -> True,
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IntAluPlugin.ALU_CTRL -> IntAluPlugin.AluCtrlEnum.ADD_SUB
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)
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val loadActions = stdActions ++ List(
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SRC2_CTRL -> Src2CtrlEnum.IMI,
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@ -143,7 +152,6 @@ class DBusCachedPlugin(config : DataCacheConfig,
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val size = input(INSTRUCTION)(13 downto 12).asUInt
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cache.io.cpu.execute.isValid := arbitration.isValid && input(MEMORY_ENABLE)
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cache.io.cpu.execute.isStuck := arbitration.isStuck
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cache.io.cpu.execute.address := input(SRC_ADD).asUInt
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cache.io.cpu.execute.args.wr := input(MEMORY_WR)
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cache.io.cpu.execute.args.data := size.mux(
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@ -194,7 +202,7 @@ class DBusCachedPlugin(config : DataCacheConfig,
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redoBranch.payload := input(PC)
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arbitration.flushAll setWhen(redoBranch.valid)
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when(cache.io.cpu.writeBack.isValid) {
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when(arbitration.isValid && input(MEMORY_ENABLE)) {
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if (catchAccessError) when(cache.io.cpu.writeBack.accessError) {
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exceptionBus.valid := True
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exceptionBus.code := (input(MEMORY_WR) ? U(7) | U(5)).resized
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@ -235,6 +243,45 @@ class DBusCachedPlugin(config : DataCacheConfig,
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}
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}
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//Share access to the dBus (used by self refilled MMU)
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val dBusSharing = (dBusAccess != null) generate pipeline plug new Area{
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dBusAccess.cmd.ready := False
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val forceDatapath = False
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when(dBusAccess.cmd.valid){
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decode.arbitration.haltByOther := True
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when(!stagesFromExecute.map(_.arbitration.isValid).orR && !pipeline.service(classOf[ExceptionService]).isExceptionPending()){
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when(!cache.io.cpu.redo) {
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cache.io.cpu.execute.isValid := True
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dBusAccess.cmd.ready := !execute.arbitration.isStuck
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}
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cache.io.cpu.execute.args.wr := dBusAccess.cmd.write
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cache.io.cpu.execute.args.data := dBusAccess.cmd.data
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cache.io.cpu.execute.args.size := dBusAccess.cmd.size
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cache.io.cpu.execute.args.forceUncachedAccess := True //TODO Cached and redo management
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if(genAtomic) cache.io.cpu.execute.args.isAtomic := False
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cache.io.cpu.execute.address := dBusAccess.cmd.address //Will only be 12 muxes
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forceDatapath := True
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}
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}
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execute.insert(IS_DBUS_SHARING) := dBusAccess.cmd.fire
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||||
|
||||
mmuBus.cmd.bypassTranslation setWhen(memory.input(IS_DBUS_SHARING))
|
||||
cache.io.cpu.memory.isValid setWhen(memory.input(IS_DBUS_SHARING))
|
||||
cache.io.cpu.writeBack.isValid setWhen(writeBack.input(IS_DBUS_SHARING))
|
||||
dBusAccess.rsp.valid := writeBack.input(IS_DBUS_SHARING) && !cache.io.cpu.writeBack.isWrite && !cache.io.cpu.writeBack.haltIt
|
||||
dBusAccess.rsp.data := cache.io.cpu.writeBack.data
|
||||
dBusAccess.rsp.error := cache.io.cpu.writeBack.unalignedAccess || cache.io.cpu.writeBack.accessError
|
||||
|
||||
component.addPrePopTask{() =>
|
||||
when(forceDatapath){
|
||||
execute.output(REGFILE_WRITE_DATA) := dBusAccess.cmd.address.asBits
|
||||
}
|
||||
memory.input(IS_DBUS_SHARING) init(False)
|
||||
writeBack.input(IS_DBUS_SHARING) init(False)
|
||||
}
|
||||
}
|
||||
|
||||
if(csrInfo){
|
||||
val csr = service(classOf[CsrPlugin])
|
||||
csr.r(0xCC0, 0 -> U(cacheSize/wayCount), 20 -> U(bytePerLine))
|
||||
|
|
|
|||
|
|
@ -21,6 +21,8 @@ class HaltOnExceptionPlugin() extends Plugin[VexRiscv] with ExceptionService {
|
|||
exceptionPortsInfos += ExceptionPortInfo(interface,stage,priority)
|
||||
interface
|
||||
}
|
||||
override def isExceptionPending(): Bool = False
|
||||
|
||||
|
||||
override def build(pipeline: VexRiscv): Unit = {
|
||||
import pipeline._
|
||||
|
|
|
|||
|
|
@ -1316,6 +1316,16 @@ public:
|
|||
if(isDBusCheckedRegion(addr)){
|
||||
CpuRef::MemWrite w;
|
||||
w.address = addr;
|
||||
while((mask & 1) == 0){
|
||||
mask >>= 1;
|
||||
w.address++;
|
||||
w.data >>= 8;
|
||||
}
|
||||
switch(mask){
|
||||
case 1: size = 0; break;
|
||||
case 3: size = min(1u, size); break;
|
||||
case 15: size = min(2u, size); break;
|
||||
}
|
||||
w.size = 1 << size;
|
||||
switch(size){
|
||||
case 0: w.data = *data & 0xFF; break;
|
||||
|
|
@ -3446,6 +3456,7 @@ int main(int argc, char **argv, char **env) {
|
|||
// redo(REDO,WorkspaceRegression("deleg").withRiscvRef()->loadHex("../raw/deleg/build/deleg.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
// return 0;
|
||||
|
||||
redo(REDO,WorkspaceRegression("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););
|
||||
|
||||
for(int idx = 0;idx < 1;idx++){
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue