Fix non RVC fetcher exception PC capture
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@ -285,7 +285,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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bufferData := input.rsp.inst(31 downto 16)
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}
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bufferValid.clearWhen(flush)
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iBusRsp.readyForError.clearWhen(bufferValid && isRvc)
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iBusRsp.readyForError.clearWhen(bufferValid && isRvc) //Can't emit error, as there is a earlier instruction pending
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incomingInstruction setWhen(bufferValid && bufferData(1 downto 0) =/= 3)
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})
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@ -294,19 +294,21 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val injector = new Area {
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val inputBeforeStage = condApply(if (decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(flush))
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if (injectorReadyCutGen) {
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iBusRsp.readyForError.clearWhen(inputBeforeStage.valid)
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iBusRsp.readyForError.clearWhen(inputBeforeStage.valid) //Can't emit error if there is a instruction pending in the s2mPipe
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incomingInstruction setWhen (inputBeforeStage.valid)
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}
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val decodeInput = (if (injectorStage) {
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val decodeInput = inputBeforeStage.m2sPipeWithFlush(flush, collapsBubble = false)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeStage.rsp.inst)
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iBusRsp.readyForError.clearWhen(decodeInput.valid)
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iBusRsp.readyForError.clearWhen(decodeInput.valid) //Can't emit error when there is a instruction pending in the injector stage buffer
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incomingInstruction setWhen (decodeInput.valid)
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decodeInput
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} else {
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inputBeforeStage
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})
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if(!decodePcGen) iBusRsp.readyForError.clearWhen(!pcValid(decode)) //Need to wait a valid PC on the decode stage, as it is use to fill CSR xEPC
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def pcUpdatedGen(input : Bool, stucks : Seq[Bool], relaxedInput : Boolean) : Seq[Bool] = {
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stucks.scanLeft(input)((i, stuck) => {
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