Fix CsrPlugin case issue
Better DBusSimplePlugin FMax with catch enables SrcPlugin can now insert SRC1 and SRC2 in the execute mode for lower area usage and combinatorial path balancing
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e9ab3d71d5
commit
8d34c04425
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@ -64,7 +64,8 @@ object GenFull extends App{
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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separatedAddSub = false,
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executeInsertion = true
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),
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new FullBarrielShifterPlugin,
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new HazardSimplePlugin(
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@ -31,7 +31,7 @@ object CsrAccess {
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}
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case class ExceptionPortInfo(port : Flow[ExceptionCause],stage : Stage, priority : Int)
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case class csrPluginConfig(
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case class CsrPluginConfig(
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catchIllegalAccess : Boolean,
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mvendorid : BigInt,
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marchid : BigInt,
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@ -55,7 +55,7 @@ case class csrPluginConfig(
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}
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object CsrPluginConfig{
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val all = csrPluginConfig(
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val all = CsrPluginConfig(
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catchIllegalAccess = true,
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mvendorid = 11,
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marchid = 22,
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@ -76,7 +76,7 @@ object CsrPluginConfig{
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ucycleAccess = CsrAccess.READ_ONLY
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)
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val small = csrPluginConfig(
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val small = CsrPluginConfig(
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catchIllegalAccess = false,
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mvendorid = null,
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marchid = null,
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@ -97,7 +97,7 @@ object CsrPluginConfig{
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ucycleAccess = CsrAccess.NONE
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)
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val smallest = csrPluginConfig(
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val smallest = CsrPluginConfig(
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catchIllegalAccess = false,
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mvendorid = null,
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marchid = null,
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@ -140,7 +140,7 @@ case class CsrMapping(){
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class CsrPlugin(config : csrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor{
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class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor{
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import config._
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import CsrAccess._
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@ -103,8 +103,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
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object MEMORY_ENABLE extends Stageable(Bool)
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object MEMORY_READ_DATA extends Stageable(Bits(32 bits))
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object MEMORY_ADDRESS_LOW extends Stageable(UInt(2 bits))
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object ALIGNEMENT_FAULT extends Stageable(Bool)
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var executeExceptionPort : Flow[ExceptionCause] = null
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var memoryExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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import Riscv._
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@ -117,7 +117,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
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SRC_USE_SUB_LESS -> False,
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MEMORY_ENABLE -> True,
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REG1_USE -> True
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) ++ (if(catchAccessFault) List(IntAluPlugin.ALU_CTRL -> IntAluPlugin.AluCtrlEnum.ADD_SUB) else Nil) //Used for access fault bad address in memory stage
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) ++ (if(catchAccessFault || catchAddressMisaligned) List(IntAluPlugin.ALU_CTRL -> IntAluPlugin.AluCtrlEnum.ADD_SUB) else Nil) //Used for access fault bad address in memory stage
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val loadActions = stdActions ++ List(
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SRC2_CTRL -> Src2CtrlEnum.IMI,
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@ -137,12 +137,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
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List(SB, SH, SW).map(_ -> storeActions)
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)
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if(catchAddressMisaligned) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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executeExceptionPort = exceptionService.newExceptionPort(pipeline.execute)
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}
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if(catchAccessFault) {
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if(catchAccessFault || catchAddressMisaligned) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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memoryExceptionPort = exceptionService.newExceptionPort(pipeline.memory)
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}
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@ -158,7 +154,14 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
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execute plug new Area{
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import execute._
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dBus.cmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers && !arbitration.removeIt
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insert(ALIGNEMENT_FAULT) := {
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if (catchAddressMisaligned)
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(dBus.cmd.size === 2 && dBus.cmd.address(1 downto 0) =/= 0) || (dBus.cmd.size === 1 && dBus.cmd.address(0 downto 0) =/= 0)
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else
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False
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}
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dBus.cmd.valid := arbitration.isValid && input(MEMORY_ENABLE) && !arbitration.isStuckByOthers && !arbitration.removeIt && !input(ALIGNEMENT_FAULT)
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dBus.cmd.wr := input(INSTRUCTION)(5)
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dBus.cmd.address := input(SRC_ADD).asUInt
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dBus.cmd.size := input(INSTRUCTION)(13 downto 12).asUInt
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@ -167,18 +170,11 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
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U(1) -> input(REG2)(15 downto 0) ## input(REG2)(15 downto 0),
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default -> input(REG2)(31 downto 0)
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)
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when(arbitration.isValid && input(MEMORY_ENABLE) && !dBus.cmd.ready){
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when(arbitration.isValid && input(MEMORY_ENABLE) && !dBus.cmd.ready && !input(ALIGNEMENT_FAULT)){
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arbitration.haltIt := True
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}
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insert(MEMORY_ADDRESS_LOW) := dBus.cmd.address(1 downto 0)
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if(catchAddressMisaligned){
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executeExceptionPort.code := (dBus.cmd.wr ? U(6) | U(4)).resized
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executeExceptionPort.badAddr := dBus.cmd.address
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executeExceptionPort.valid := (arbitration.isValid && input(MEMORY_ENABLE)
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&& ((dBus.cmd.size === 2 && dBus.cmd.address(1 downto 0) =/= 0) || (dBus.cmd.size === 1 && dBus.cmd.address(0 downto 0) =/= 0)))
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}
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}
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//Collect dBus.rsp read responses
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@ -189,12 +185,28 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
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insert(MEMORY_READ_DATA) := dBus.rsp.data
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arbitration.haltIt setWhen(arbitration.isValid && input(MEMORY_ENABLE) && input(REGFILE_WRITE_VALID) && !dBus.rsp.ready)
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if(catchAccessFault){
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memoryExceptionPort.valid := arbitration.isValid && input(MEMORY_ENABLE) && dBus.rsp.ready && dBus.rsp.error
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if(catchAccessFault || catchAddressMisaligned){
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if(!catchAccessFault){
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memoryExceptionPort.code := (input(INSTRUCTION)(5) ? U(6) | U(4)).resized
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memoryExceptionPort.valid := input(ALIGNEMENT_FAULT)
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} else if(!catchAddressMisaligned){
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memoryExceptionPort.valid := dBus.rsp.ready && dBus.rsp.error
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memoryExceptionPort.code := 5
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} else {
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memoryExceptionPort.valid := dBus.rsp.ready && dBus.rsp.error
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memoryExceptionPort.code := 5
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when(input(ALIGNEMENT_FAULT)){
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memoryExceptionPort.code := (input(INSTRUCTION)(5) ? U(6) | U(4)).resized
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memoryExceptionPort.valid := True
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}
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}
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when(!(arbitration.isValid && input(MEMORY_ENABLE))){
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memoryExceptionPort.valid := False
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}
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memoryExceptionPort.badAddr := input(REGFILE_WRITE_DATA).asUInt //Drived by IntAluPlugin
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}
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assert(!(dBus.rsp.ready && input(MEMORY_ENABLE) && arbitration.isValid && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
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}
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@ -80,6 +80,15 @@ class FullBarrielShifterPlugin extends Plugin[VexRiscv]{
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}
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}
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class LightShifterPlugin extends Plugin[VexRiscv]{
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object ShiftCtrlEnum extends SpinalEnum(binarySequential){
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val DISABLE, SLL, SRL, SRA = newElement()
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@ -4,13 +4,13 @@ import VexRiscv.{Riscv, VexRiscv}
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import spinal.core._
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class SrcPlugin(separatedAddSub : Boolean) extends Plugin[VexRiscv]{
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class SrcPlugin(separatedAddSub : Boolean, executeInsertion : Boolean = false) extends Plugin[VexRiscv]{
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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decode plug new Area{
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import decode._
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val insertionStage = if(executeInsertion) execute else decode
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insertionStage plug new Area{
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import insertionStage._
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val imm = Riscv.IMM(input(INSTRUCTION))
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insert(SRC1) := input(SRC1_CTRL).mux(
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@ -209,8 +209,8 @@ class Briey(config: BrieyConfig) extends Component{
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// )
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),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = false,
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// catchAccessFault = false
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// catchAddressMisaligned = true,
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// catchAccessFault = true
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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@ -242,7 +242,8 @@ class Briey(config: BrieyConfig) extends Component{
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false
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separatedAddSub = false,
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executeInsertion = true
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),
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new FullBarrielShifterPlugin,
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new MulPlugin,
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@ -263,7 +264,7 @@ class Briey(config: BrieyConfig) extends Component{
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prediction = STATIC
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),
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new CsrPlugin(
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config = csrPluginConfig(
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config = CsrPluginConfig(
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catchIllegalAccess = false,
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mvendorid = null,
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marchid = null,
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@ -412,7 +412,6 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val mmuRsp = RegNextWhen(io.cpu.fetch.mmuBus.rsp,!io.cpu.decode.isStuck)
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val hit = tag.valid && tag.address === mmuRsp.physicalAddress(tagRange) && !(tag.loading && !lineLoader.loadedWords(mmuRsp.physicalAddress(wordRange)))
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// val hit = tag.hit && !(tag.loading && !lineLoader.loadedWords(mmuRsp.physicalAddress(wordRange)))
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io.cpu.decode.haltIt := io.cpu.decode.isValid && !hit //TODO PERF not halit it when removed, Should probably be applyed in many other places
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io.cpu.decode.data := data
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