Fix RVC step by step triggering next instruction branch predictor
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6326736401
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8df2dcbd40
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@ -17,6 +17,7 @@ trait IBusFetcher{
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def pcValid(stage : Stage) : Bool
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def getInjectionPort() : Stream[Bits]
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def withRvc() : Boolean
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def forceNoDecode() : Unit
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}
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@ -319,6 +319,10 @@ class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount :
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if(pipeline.config.withRvc){
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val cleanStep = RegNext(stepIt && decode.arbitration.isFiring) init(False)
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execute.arbitration.flushNext setWhen(cleanStep)
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when(cleanStep){
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execute.arbitration.flushNext := True
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iBusFetcher.forceNoDecode()
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}
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}
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io.resetOut := RegNext(resetIt)
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@ -33,6 +33,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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// assert(!(cmdToRspStageCount == 1 && !injectorStage))
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assert(!(compressedGen && !decodePcGen))
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var fetcherHalt : Bool = null
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var forceNoDecodeCond : Bool = null
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var pcValids : Vec[Bool] = null
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def pcValid(stage : Stage) = pcValids(pipeline.indexOf(stage))
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var incomingInstruction : Bool = null
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@ -50,6 +51,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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var predictionJumpInterface : Flow[UInt] = null
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override def haltIt(): Unit = fetcherHalt := True
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override def forceNoDecode(): Unit = forceNoDecodeCond := True
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case class JumpInfo(interface : Flow[UInt], stage: Stage, priority : Int)
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val jumpInfos = ArrayBuffer[JumpInfo]()
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override def createJumpInterface(stage: Stage, priority : Int = 0): Flow[UInt] = {
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@ -63,6 +65,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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// var decodeExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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fetcherHalt = False
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forceNoDecodeCond = False
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incomingInstruction = False
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if(resetVector == null) externalResetVector = in(UInt(32 bits).setName("externalResetVector"))
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@ -408,6 +411,9 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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})
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}
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Component.current.addPrePopTask(() => {
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decode.arbitration.isValid clearWhen(forceNoDecodeCond)
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})
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//Formal verification signals generation, miss prediction stuff ?
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val formal = new Area {
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