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more litex smp cluster pipelining

This commit is contained in:
Dolu1990 2020-05-07 13:18:11 +02:00
parent fc0f3a2020
commit 8e025aeeaa
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
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@ -305,7 +305,7 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
capabilities = Seq(iBusArbiterParameter, iBusArbiterParameter), capabilities = Seq(iBusArbiterParameter, iBusArbiterParameter),
pendingMax = 15 pendingMax = 15
) )
iBusDecoder.io.input << iBusArbiter.io.output iBusDecoder.io.input << iBusArbiter.io.output.pipelined(cmdValid = true)
val iMem = LiteDramNative(p.liteDram) val iMem = LiteDramNative(p.liteDram)
val iMemBridge = iMem.fromBmb(iBusDecoder.io.outputs(1), wdataFifoSize = 0, rdataFifoSize = 32) val iMemBridge = iMem.fromBmb(iBusDecoder.io.outputs(1), wdataFifoSize = 0, rdataFifoSize = 32)
@ -350,8 +350,8 @@ object VexRiscvLitexSmpClusterGen extends App {
debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")) debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
) )
SpinalVerilog(Bench.compressIo(dutGen)) // SpinalVerilog(Bench.compressIo(dutGen))
// SpinalVerilog(dutGen) SpinalVerilog(dutGen)
} }