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VexRiscv
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Got the debug plugin working with the linux config (had to disable CSR ebreak)

This commit is contained in:
Charles Papon 2019-04-05 00:25:27 +02:00
parent 4f0a02594c
commit 8e6010fd71
3 changed files with 8 additions and 8 deletions
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11
src/main/scala/vexriscv/demo/Linux.scala
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@ -40,13 +40,13 @@ cd VexRiscv
Run regressions => Run regressions =>
sbt "runMain vexriscv.demo.LinuxGen -r" sbt "runMain vexriscv.demo.LinuxGen -r"
cd src/test/cpp/regression cd src/test/cpp/regression
make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=no DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=10 TRACE=no make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=10 TRACE=no
Run linux in simulation (Require the machime mode emulator compiled in SIM mode) => Run linux in simulation (Require the machime mode emulator compiled in SIM mode) =>
sbt "runMain vexriscv.demo.LinuxGen" sbt "runMain vexriscv.demo.LinuxGen"
cd src/test/cpp/regression cd src/test/cpp/regression
export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=no SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/vmlinux.bin DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=no make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX=$BUILDROOT/output/images/vmlinux.bin DTB=$BUILDROOT/board/spinal/vexriscv_sim/rv32.dtb RAMDISK=$BUILDROOT/output/images/rootfs.cpio TRACE=no FLOW_INFO=no
Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode) Run linux with QEMU (Require the machime mode emulator compiled in QEMU mode)
export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal export BUILDROOT=/home/miaou/pro/riscv/buildrootSpinal
@ -88,6 +88,7 @@ https://github.com/riscv/riscv-qemu/wiki#build-and-install
*/ */
//TODO test dcache flush
//TODO have to check, look like supervisor can't get interrupt if the machine mod didn't delegated it, have to check exactly //TODO have to check, look like supervisor can't get interrupt if the machine mod didn't delegated it, have to check exactly
object LinuxGen { object LinuxGen {
def configFull(litex : Boolean, withMmu : Boolean) = { def configFull(litex : Boolean, withMmu : Boolean) = {
@ -178,7 +179,7 @@ object LinuxGen {
), ),
new RegFilePlugin( new RegFilePlugin(
regFileReadyKind = plugin.SYNC, regFileReadyKind = plugin.SYNC,
zeroBoot = false //TODO zeroBoot = true //TODO
), ),
new IntAluPlugin, new IntAluPlugin,
new SrcPlugin( new SrcPlugin(
@ -205,7 +206,7 @@ object LinuxGen {
divUnrollFactor = 1 divUnrollFactor = 1
), ),
// new DivPlugin, // new DivPlugin,
new CsrPlugin(CsrPluginConfig.linux(0x80000020l)), new CsrPlugin(CsrPluginConfig.linux(0x80000020l).copy(ebreakGen = false)),
// new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/* // new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/*
// CsrPluginConfig( // CsrPluginConfig(
// catchIllegalAccess = false, // catchIllegalAccess = false,
@ -229,7 +230,7 @@ object LinuxGen {
// wfiGenAsNop = true, // wfiGenAsNop = true,
// ucycleAccess = CsrAccess.NONE // ucycleAccess = CsrAccess.NONE
// )), // )),
// new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
new BranchPlugin( new BranchPlugin(
earlyBranch = false, earlyBranch = false,
catchAddressMisaligned = true, catchAddressMisaligned = true,

3
src/test/cpp/regression/main.cpp
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@ -3567,8 +3567,7 @@ int main(int argc, char **argv, char **env) {
#endif #endif
#ifdef DEBUG_PLUGIN #ifdef DEBUG_PLUGIN
//TODO redo(REDO,DebugPluginTest().run(1e6););
// redo(REDO,DebugPluginTest().run(1e6););
#endif #endif
#endif #endif

2
src/test/scala/vexriscv/DhrystoneBench.scala
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@ -92,7 +92,7 @@ class DhrystoneBench extends FunSuite{
getDmips( getDmips(
name = "GenFull", name = "GenFull",
gen = GenFull.main(null), gen = GenFull.main(null),
testCmd = "make clean run REDO=10 CSR=no" testCmd = "make clean run REDO=10 CSR=no MMU=no"
) )
test("final_report") { test("final_report") {