fpu wip
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@ -15,6 +15,8 @@ case class FpuCore(p : FpuParameter) extends Component{
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val port = slave(FpuPort(p))
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}
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// val commitPerSourceCount = 8
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val rfLockCount = 5
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val lockIdType = HardType(UInt(log2Up(rfLockCount) bits))
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@ -89,11 +91,44 @@ case class FpuCore(p : FpuParameter) extends Component{
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val valid = RegInit(False)
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val source = Reg(p.source)
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val address = Reg(p.rfAddress)
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val id = Reg(UInt(log2Up(rfLockCount) bits))
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val commited = Reg(Bool)
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val write = Reg(Bool)
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}
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val lockFree = !lock.map(_.valid).andR
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val lockFreeId = OHMasking.first(lock.map(!_.valid))
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}
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val commitLogic = for(source <- 0 until p.sourceCount) yield new Area{
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val fire = False
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val target, hit = Reg(UInt(log2Up(rfLockCount) bits)) init(0)
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when(fire){
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hit := hit + 1
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}
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io.port.commit(source).ready := False
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when(io.port.commit(source).valid) {
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for (lock <- rf.lock) {
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when(lock.valid && lock.source === source && lock.id === hit) {
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fire := True
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lock.commited := True
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lock.write := io.port.commit(source).write
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io.port.commit(source).ready := True
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}
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}
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}
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}
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// case class CommitLine() extends Bundle{
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// val valid = Bool()
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// val write = Bool()
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// }
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// val commits = for(i <- 0 until p.sourceCount) yield new Area{
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// val lines = Vec(CommitLine(), commitPerSourceCount)
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// lines.foreach(_.valid init(False))
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//
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// }
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val read = new Area{
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val s0 = Stream(RfReadInput())
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s0.arbitrationFrom(io.port.cmd)
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@ -137,11 +172,17 @@ case class FpuCore(p : FpuParameter) extends Component{
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val hits = List((useRs1, s0.rs1), (useRs2, s0.rs2), (useRs3, s0.rs3), (useRd, s0.rd)).map{case (use, reg) => use && rf.lock.map(l => l.valid && l.source === s0.source && l.address === reg).orR}
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val hazard = hits.orR
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when(s0.fire && useRd){
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for(i <- 0 until p.sourceCount){
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when(s0.source === i){
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commitLogic(i).target := commitLogic(i).target + 1
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}
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}
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for(i <- 0 until rfLockCount){
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when(rf.lockFreeId(i)){
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rf.lock(i).valid := True
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rf.lock(i).source := s0.source
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rf.lock(i).address := s0.rd
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rf.lock(i).id := commitLogic.map(_.target).read(s0.source)
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}
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}
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}
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@ -224,9 +265,16 @@ case class FpuCore(p : FpuParameter) extends Component{
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}
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val load = new Area{
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def input = decode.load
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val output = input.stage()
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val input = decode.load.stage()
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def feed = io.port.load(input.source)
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val hazard = !feed.valid
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val output = input.haltWhen(hazard).swapPayload(WriteInput())
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io.port.load.foreach(_.ready := False)
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feed.ready := input.valid && output.ready
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output.source := input.source
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output.lockId := input.lockId
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output.rd := input.rd
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output.value.assignFromBits(feed.value)
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}
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@ -506,47 +554,20 @@ case class FpuCore(p : FpuParameter) extends Component{
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val write = new Area{
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val port = rf.ram.writePort
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port.valid := False
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port.payload.assignDontCare()
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val arbitrated = StreamArbiterFactory.lowerFirst.noLock.on(List(load.output, add.output, mul.output))
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val isCommited = rf.lock.map(_.commited).read(arbitrated.lockId)
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val commited = arbitrated.haltWhen(!isCommited).toFlow
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val lockFree = Flow(lockIdType)
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lockFree.valid := port.fire
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lockFree.payload.assignDontCare()
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load.output.ready := False
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mul.output.ready := False
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add.output.ready := True
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io.port.commit.ready := False
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when(add.output.valid) {
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port.valid := True
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port.address := add.output.source @@ add.output.rd
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port.data := add.output.value
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lockFree.payload := add.output.lockId
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} elsewhen(mul.output.valid) {
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port.valid := True
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port.address := mul.output.source @@ mul.output.rd
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port.data := mul.output.value
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mul.output.ready := True
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lockFree.payload := mul.output.lockId
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} elsewhen(load.output.valid && io.port.commit.valid) {
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port.valid := io.port.commit.write
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port.address := load.output.source @@ load.output.rd
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port.data.assignFromBits(io.port.commit.value)
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load.output.ready := True
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io.port.commit.ready := True
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lockFree.payload := load.output.lockId
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}
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when(lockFree.fire){
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for(i <- 0 until rfLockCount) when(lockFree.payload === i){
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when(commited.valid){
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for(i <- 0 until rfLockCount) when(commited.lockId === i){
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rf.lock(i).valid := False
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}
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}
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val port = rf.ram.writePort
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port.valid := commited.valid && rf.lock.map(_.write).read(commited.lockId)
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port.address := commited.source @@ commited.rd
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port.data := commited.value
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}
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}
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@ -572,7 +593,7 @@ object FpuSynthesisBench extends App{
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FpuParameter(
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internalMantissaSize = 23,
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withDouble = false,
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sourceWidth = 0
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sourceCount = 1
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)
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)
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rtls += new Fpu(
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@ -580,7 +601,7 @@ object FpuSynthesisBench extends App{
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FpuParameter(
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internalMantissaSize = 52,
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withDouble = true,
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sourceWidth = 0
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sourceCount = 1
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)
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)
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@ -22,13 +22,18 @@ case class FpuFloat(exponentSize: Int,
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val sign = Bool
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}
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case class FpuOpcode(p : FpuParameter) extends SpinalEnum{
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object FpuOpcode extends SpinalEnum{
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val LOAD, STORE, MUL, ADD, FMA, I2F, F2I, CMP, DIV, SQRT = newElement()
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}
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object FpuFormat extends SpinalEnum{
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val FLOAT, DOUBLE = newElement()
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}
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case class FpuParameter( internalMantissaSize : Int,
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withDouble : Boolean,
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sourceWidth : Int){
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sourceCount : Int){
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val storeLoadType = HardType(Bits(if(withDouble) 64 bits else 32 bits))
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val internalExponentSize = if(withDouble) 11 else 8
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@ -37,11 +42,9 @@ case class FpuParameter( internalMantissaSize : Int,
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val source = HardType(UInt(sourceWidth bits))
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val rfAddress = HardType(UInt(5 bits))
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val Opcode = new FpuOpcode(this)
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val Format = new SpinalEnum{
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val FLOAT = newElement()
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val DOUBLE = withDouble generate newElement()
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}
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val Opcode = FpuOpcode
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val Format = FpuFormat
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val sourceWidth = log2Up(sourceCount)
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}
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case class FpuCmd(p : FpuParameter) extends Bundle{
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@ -55,9 +58,11 @@ case class FpuCmd(p : FpuParameter) extends Bundle{
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}
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case class FpuCommit(p : FpuParameter) extends Bundle{
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val source = UInt(p.sourceWidth bits)
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val write = Bool()
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val value = p.storeLoadType() // IEEE 754 load
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}
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case class FpuLoad(p : FpuParameter) extends Bundle{
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val value = p.storeLoadType() // IEEE 754
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}
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case class FpuRsp(p : FpuParameter) extends Bundle{
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@ -67,11 +72,13 @@ case class FpuRsp(p : FpuParameter) extends Bundle{
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case class FpuPort(p : FpuParameter) extends Bundle with IMasterSlave {
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val cmd = Stream(FpuCmd(p))
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val commit = Stream(FpuCommit(p))
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val commit = Vec(Stream(FpuCommit(p)), p.sourceCount)
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val load = Vec(Stream(FpuLoad(p)), p.sourceCount)
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val rsp = Stream(FpuRsp(p))
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override def asMaster(): Unit = {
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master(cmd, commit)
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master(cmd)
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(commit ++ load).foreach(master(_))
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slave(rsp)
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}
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}
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@ -19,7 +19,7 @@ class FpuTest extends FunSuite{
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val p = FpuParameter(
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internalMantissaSize = 23,
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withDouble = false,
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sourceWidth = 0
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sourceCount = 1
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)
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SimConfig.withFstWave.compile(new FpuCore(p)).doSim(seed = 42){ dut =>
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@ -31,8 +31,23 @@ class FpuTest extends FunSuite{
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val cpus = for(id <- 0 until 1 << p.sourceWidth) yield new {
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val cmdQueue = mutable.Queue[FpuCmd => Unit]()
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val commitQueue = mutable.Queue[FpuCommit => Unit]()
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val loadQueue = mutable.Queue[FpuLoad => Unit]()
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val rspQueue = mutable.Queue[FpuRsp => Unit]()
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StreamDriver(dut.io.port.commit(id) ,dut.clockDomain){payload =>
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if(commitQueue.isEmpty) false else {
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commitQueue.dequeue().apply(payload)
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true
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}
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}
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StreamDriver(dut.io.port.load(id) ,dut.clockDomain){payload =>
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if(loadQueue.isEmpty) false else {
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loadQueue.dequeue().apply(payload)
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true
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}
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}
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def loadRaw(rd : Int, value : BigInt): Unit ={
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cmdQueue += {cmd =>
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cmd.source #= id
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@ -44,8 +59,9 @@ class FpuTest extends FunSuite{
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cmd.rd #= rd
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}
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commitQueue += {cmd =>
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cmd.source #= id
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cmd.write #= true
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}
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loadQueue += {cmd =>
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cmd.value #= value
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}
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}
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@ -82,6 +98,9 @@ class FpuTest extends FunSuite{
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cmd.rs3.randomize()
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cmd.rd #= rd
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}
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commitQueue += {cmd =>
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cmd.write #= true
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}
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}
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def add(rd : Int, rs1 : Int, rs2 : Int): Unit ={
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@ -94,6 +113,9 @@ class FpuTest extends FunSuite{
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cmd.rs3.randomize()
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cmd.rd #= rd
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}
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commitQueue += {cmd =>
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cmd.write #= true
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}
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}
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def div(rd : Int, rs1 : Int, rs2 : Int): Unit ={
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@ -106,6 +128,9 @@ class FpuTest extends FunSuite{
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cmd.rs3.randomize()
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cmd.rd #= rd
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}
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commitQueue += {cmd =>
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cmd.write #= true
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}
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}
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def sqrt(rd : Int, rs1 : Int): Unit ={
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@ -118,6 +143,9 @@ class FpuTest extends FunSuite{
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cmd.rs3.randomize()
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cmd.rd #= rd
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}
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commitQueue += {cmd =>
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cmd.write #= true
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}
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}
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def fma(rd : Int, rs1 : Int, rs2 : Int, rs3 : Int): Unit ={
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@ -130,6 +158,9 @@ class FpuTest extends FunSuite{
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cmd.rs3 #= rs3
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cmd.rd #= rd
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}
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commitQueue += {cmd =>
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cmd.write #= true
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}
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}
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}
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@ -143,15 +174,7 @@ class FpuTest extends FunSuite{
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}
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}
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StreamDriver(dut.io.port.commit ,dut.clockDomain){payload =>
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cpus.map(_.commitQueue).filter(_.nonEmpty).toSeq match {
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case Nil => false
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case l => {
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l.randomPick().dequeue().apply(payload)
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true
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}
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}
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}
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StreamMonitor(dut.io.port.rsp, dut.clockDomain){payload =>
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@ -272,6 +295,7 @@ class FpuTest extends FunSuite{
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val b2f = lang.Float.intBitsToFloat(_)
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testAdd(0.1f, 1.6f)
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testSqrt(1.5625f)
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testSqrt(1.5625f*2)
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@ -289,7 +313,6 @@ class FpuTest extends FunSuite{
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// dut.clockDomain.waitSampling(1000)
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// simFailure()
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testAdd(0.1f, 1.6f)
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testMul(0.1f, 1.6f)
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testFma(1.1f, 2.2f, 3.0f)
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testDiv(1.0f, 1.1f)
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