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Disable MMU in machine mode

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This commit is contained in:
Dolu1990 2019-03-19 22:21:30 +01:00
parent 3fbc2f4458
commit 8f22365959
4 changed files with 13 additions and 6 deletions
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2
src/main/scala/vexriscv/Services.scala
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@ -37,10 +37,12 @@ trait ExceptionService{
trait PrivilegeService{ trait PrivilegeService{
def isUser(stage : Stage) : Bool def isUser(stage : Stage) : Bool
def isMachine(stage : Stage) : Bool
} }
case class PrivilegeServiceDefault() extends PrivilegeService{ case class PrivilegeServiceDefault() extends PrivilegeService{
override def isUser(stage: Stage): Bool = False override def isUser(stage: Stage): Bool = False
override def isMachine(stage: Stage): Bool = True
} }
trait InterruptionInhibitor{ trait InterruptionInhibitor{

2
src/main/scala/vexriscv/demo/Linux.scala
View file

@ -108,7 +108,7 @@ object LinuxGen {
catchIllegalInstruction = true catchIllegalInstruction = true
), ),
new RegFilePlugin( new RegFilePlugin(
regFileReadyKind = plugin.ASYNC, regFileReadyKind = plugin.SYNC,
zeroBoot = true zeroBoot = true
), ),
new IntAluPlugin, new IntAluPlugin,

3
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View file

@ -362,7 +362,8 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
def inhibateInterrupts() : Unit = allowInterrupts := False def inhibateInterrupts() : Unit = allowInterrupts := False
def inhibateException() : Unit = allowException := False def inhibateException() : Unit = allowException := False
def isUser(stage : Stage) : Bool = privilege === 0 override def isUser(stage : Stage) : Bool = privilege === 0
override def isMachine(stage: Stage): Bool = privilege === 3
override def build(pipeline: VexRiscv): Unit = { override def build(pipeline: VexRiscv): Unit = {
import pipeline._ import pipeline._

12
src/main/scala/vexriscv/plugin/MmuPlugin.scala
View file

@ -39,7 +39,8 @@ case class MmuPortConfig(portTlbSize : Int)
class MmuPlugin(virtualRange : UInt => Bool, class MmuPlugin(virtualRange : UInt => Bool,
ioRange : UInt => Bool, ioRange : UInt => Bool,
allowUserIo : Boolean) extends Plugin[VexRiscv] with MemoryTranslator { allowUserIo : Boolean,
allowMachineModeMmu : Boolean = false) extends Plugin[VexRiscv] with MemoryTranslator {
var dBus : DBusAccess = null var dBus : DBusAccess = null
val portsInfo = ArrayBuffer[MmuPort]() val portsInfo = ArrayBuffer[MmuPort]()
@ -91,11 +92,13 @@ class MmuPlugin(virtualRange : UInt => Bool,
val cacheHits = cache.map(line => line.valid && line.virtualAddress === port.bus.cmd.virtualAddress(31 downto 12)) val cacheHits = cache.map(line => line.valid && line.virtualAddress === port.bus.cmd.virtualAddress(31 downto 12))
val cacheHit = cacheHits.asBits.orR val cacheHit = cacheHits.asBits.orR
val cacheLine = MuxOH(cacheHits, cache) val cacheLine = MuxOH(cacheHits, cache)
val isInMmuRange = virtualRange(port.bus.cmd.virtualAddress) && !port.bus.cmd.bypassTranslation val privilegeService = pipeline.serviceElse(classOf[PrivilegeService], PrivilegeServiceDefault())
val entryToReplace = Counter(port.args.portTlbSize) val entryToReplace = Counter(port.args.portTlbSize)
val requireMmuLockup = virtualRange(port.bus.cmd.virtualAddress) && !port.bus.cmd.bypassTranslation
if(!allowMachineModeMmu) requireMmuLockup clearWhen(privilegeService.isMachine(execute))
when(isInMmuRange) { when(requireMmuLockup) {
port.bus.rsp.physicalAddress := cacheLine.physicalAddress @@ port.bus.cmd.virtualAddress(11 downto 0) port.bus.rsp.physicalAddress := cacheLine.physicalAddress @@ port.bus.cmd.virtualAddress(11 downto 0)
port.bus.rsp.allowRead := cacheLine.allowRead port.bus.rsp.allowRead := cacheLine.allowRead
port.bus.rsp.allowWrite := cacheLine.allowWrite port.bus.rsp.allowWrite := cacheLine.allowWrite
@ -103,7 +106,6 @@ class MmuPlugin(virtualRange : UInt => Bool,
port.bus.rsp.allowUser := cacheLine.allowUser port.bus.rsp.allowUser := cacheLine.allowUser
port.bus.rsp.exception := cacheHit && cacheLine.exception port.bus.rsp.exception := cacheHit && cacheLine.exception
port.bus.rsp.refilling := !cacheHit port.bus.rsp.refilling := !cacheHit
} otherwise { } otherwise {
port.bus.rsp.physicalAddress := port.bus.cmd.virtualAddress port.bus.rsp.physicalAddress := port.bus.cmd.virtualAddress
port.bus.rsp.allowRead := True port.bus.rsp.allowRead := True
@ -122,6 +124,8 @@ class MmuPlugin(virtualRange : UInt => Bool,
val satp = new Area { val satp = new Area {
val mode = RegInit(False) val mode = RegInit(False)
val ppn = Reg(UInt(20 bits)) val ppn = Reg(UInt(20 bits))
ports.foreach(_.requireMmuLockup clearWhen(!mode))
} }
csrService.rw(CSR.SATP, 31 -> satp.mode, 0 -> satp.ppn) //TODO write only ? csrService.rw(CSR.SATP, 31 -> satp.mode, 0 -> satp.ppn) //TODO write only ?
val State = new SpinalEnum{ val State = new SpinalEnum{