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VexRiscv
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Much better decoder using Quine-Mc Cluskey

This commit is contained in:
Charles Papon 2017-04-02 21:05:25 +02:00
parent a9f7177181
commit 8ff05bd2a8
12 changed files with 193 additions and 174 deletions
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12
src/main/scala/SpinalRiscv/Plugin/BranchPlugin.scala
View File

@ -36,7 +36,6 @@ class BranchPlugin(earlyBranch : Boolean,
val decoderService = pipeline.service(classOf[DecoderService])
val bActions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.RS,
SRC_USE_SUB_LESS -> True,
@ -45,7 +44,6 @@ class BranchPlugin(earlyBranch : Boolean,
)
val jActions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.FOUR,
SRC2_CTRL -> Src2CtrlEnum.PC,
SRC_USE_SUB_LESS -> False,
@ -157,11 +155,11 @@ class BranchPlugin(earlyBranch : Boolean,
val readAddress = prefetch.output(PC)(2, historyRamSizeLog2 bits)
fetch.insert(HISTORY_LINE) := historyCache.readSync(readAddress,!prefetch.arbitration.isStuckByOthers)
//WriteFirst bypass
val writePortReg = RegNext(historyCacheWrite)
when(writePortReg.valid && writePortReg.address === readAddress){
fetch.insert(HISTORY_LINE) := writePortReg.data
}
//WriteFirst bypass TODO long combinatorial path
// val writePortReg = RegNext(historyCacheWrite)
// when(writePortReg.valid && writePortReg.address === readAddress){
// fetch.insert(HISTORY_LINE) := writePortReg.data
// }
}
//Branch JAL, predict Bxx and branch it

4
src/main/scala/SpinalRiscv/Plugin/DBusCachedPlugin.scala
View File

@ -33,7 +33,6 @@ class DBusCachedPlugin(config : DataCacheConfig) extends Plugin[VexRiscv]{
val decoderService = pipeline.service(classOf[DecoderService])
val stdActions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC_USE_SUB_LESS -> False,
MEMORY_ENABLE -> True,
@ -523,8 +522,6 @@ class DataCache(p : DataCacheConfig) extends Component{
cpuRspIn.fromBypass := True
io.cpu.memory.haltIt.clearWhen(io.mem.cmd.fire)
} otherwise {
io.cpu.memory.haltIt := True //TODO redondent ?
}
} otherwise {
when(waysHitValid && !loadingDone) { // !loadingDone => don't solve the request directly after loader (data write to read latency)
@ -547,7 +544,6 @@ class DataCache(p : DataCacheConfig) extends Component{
io.cpu.memory.haltIt.clearWhen(cpuRspIn.ready && !victim.dataReadCmdOccureLast) //dataReadCmdOccure to avoid the case where flush,then read will victim use data read
}
} otherwise {
io.cpu.memory.haltIt := True //Exit this state automaticly (tags read port write first logic) TODO redondent ?
loaderValid := !loadingDone && !(!victimSent && victim.request.isStall) //Wait previous victim request to be completed
when(writebackWayInfo.used && writebackWayInfo.dirty) {
victim.requestIn.valid := !victimSent

1
src/main/scala/SpinalRiscv/Plugin/DBusSimplePlugin.scala
View File

@ -50,7 +50,6 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean, catchAccessFault : Bool
val decoderService = pipeline.service(classOf[DecoderService])
val stdActions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC_USE_SUB_LESS -> False,
MEMORY_ENABLE -> True,

159
src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala
View File

@ -4,12 +4,35 @@ import SpinalRiscv._
import spinal.core._
import spinal.lib._
import scala.Predef.assert
import scala.collection.mutable
import scala.collection.mutable.ArrayBuffer
case class Masked(value : BigInt,care : BigInt){
var isPrime = true
def intersects(x: Masked) = ((value ^ x.value) & care & x.care) == 0
def setPrime(value : Boolean) = {
isPrime = value
this
}
def merge(x: Masked) = {
isPrime = false
x.isPrime = false
val bit = value - x.value
new Masked(value &~ bit, care & ~bit)
}
def similar(x: Masked) = {
val diff = value - x.value
care == x.care && value > x.value && (diff & diff - 1) == 0
}
def === (hard : Bits) : Bool = (hard & care) === (value & care)
def toString(bitCount : Int) = (0 until bitCount).map(i => if(care.testBit(i)) (if(value.testBit(i)) "1" else "0") else "-").reverseIterator.reduce(_+_)
}
class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexRiscv] with DecoderService {
@ -36,9 +59,6 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
override def setup(pipeline: VexRiscv): Unit = {
import pipeline.config._
addDefault(LEGAL_INSTRUCTION, False)
if(catchIllegalInstruction) {
val exceptionService = pipeline.plugins.filter(_.isInstanceOf[ExceptionService]).head.asInstanceOf[ExceptionService]
decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode).setName("decodeExceptionPort")
@ -75,15 +95,16 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
//Build spec
val spec = encodings.map { case (key, values) =>
var decodedValue, decodedCare = BigInt(0)
var decodedValue = defaultValue
var decodedCare = defaultCare
for((e, literal) <- values){
literal.input match{
case literal : EnumLiteral[_] => literal.fixEncoding(e.dataType.asInstanceOf[SpinalEnumCraft[_]].getEncoding)
case _ =>
}
val offset = offsetOf(e)
decodedValue += literal.input.asInstanceOf[Literal].getValue << offset
decodedCare += ((BigInt(1) << e.dataType.getBitsWidth)-1) << offset
decodedValue |= literal.input.asInstanceOf[Literal].getValue << offset
decodedCare |= ((BigInt(1) << e.dataType.getBitsWidth)-1) << offset
}
(Masked(key.value,key.careAbout),Masked(decodedValue,decodedCare))
}
@ -92,7 +113,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
// logic implementation
val decodedBits = Bits(stageables.foldLeft(0)(_ + _.dataType.getBitsWidth) bits)
val defaultBits = cloneOf(decodedBits)
// val defaultBits = cloneOf(decodedBits)
// assert(defaultValue == 0)
// defaultBits := defaultValue
@ -101,16 +122,23 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
// decodedBits := logicOr.foldLeft(defaultBits)(_ | _)
for(i <- decodedBits.range)
if(defaultCare.testBit(i))
defaultBits(i) := Bool(defaultValue.testBit(i))
else
defaultBits(i).assignDontCare()
// for(i <- decodedBits.range)
// if(defaultCare.testBit(i))
// defaultBits(i) := Bool(defaultValue.testBit(i))
// else
// defaultBits(i).assignDontCare()
val logicOr = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) & key.care) === (key.value & key.care)), B(mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits))
val logicAnd = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) & key.care) === (key.value & key.care)), B(~mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits))
decodedBits := (defaultBits | logicOr.foldLeft(B(0, decodedBits.getWidth bits))(_ | _)) & ~logicAnd.foldLeft(B(0, decodedBits.getWidth bits))(_ | _)
// val logicOr = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) & key.care) === (key.value & key.care)), B(mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits))
// val logicAnd = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) & key.care) === (key.value & key.care)), B(~mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits))
// decodedBits := (defaultBits | logicOr.foldLeft(B(0, decodedBits.getWidth bits))(_ | _)) & ~logicAnd.foldLeft(B(0, decodedBits.getWidth bits))(_ | _)
// if(catchIllegalInstruction){
// insert(LEGAL_INSTRUCTION) := (for((key, mapping) <- spec) yield ((input(INSTRUCTION) & key.care) === (key.value & key.care))).reduce(_ || _)
// }
decodedBits := Symplify(input(INSTRUCTION),spec, decodedBits.getWidth)
if(catchIllegalInstruction) insert(LEGAL_INSTRUCTION) := Symplify.logicOf(input(INSTRUCTION), SymplifyBit.getPrimeImplicants(spec.unzip._1.toSeq, 32))
//Unpack decodedBits and insert fields in the pipeline
@ -135,8 +163,105 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR
toplevel.getAllIo.toList.foreach(_.asDirectionLess())
toplevel.decode.input(INSTRUCTION) := Delay((in Bits(32 bits)).setName("instruction"),2)
val stageables = encodings.flatMap(_._2.map(_._1)).toSet
stageables.foreach(e => out(Delay(toplevel.decode.insert(e),2)).setName(e.getName))
stageables.foreach(e => out(RegNext(RegNext(toplevel.decode.insert(e)).setName(e.getName()))))
if(catchIllegalInstruction) out(RegNext(RegNext(toplevel.decode.insert(LEGAL_INSTRUCTION)).setName(LEGAL_INSTRUCTION.getName())))
toplevel.getAdditionalNodesRoot.clear()
}
}
}
object Symplify{
val cache = mutable.HashMap[Bits,mutable.HashMap[Masked,Bool]]();
def getCache(addr : Bits) = cache.getOrElseUpdate(addr,mutable.HashMap[Masked,Bool]())
def logicOf(addr : Bits,terms : Seq[Masked]) = terms.map(t => getCache(addr).getOrElseUpdate(t,t === addr)).asBits.orR
def apply(addr: Bits, mapping: Iterable[(Masked, Masked)],resultWidth : Int) : Bits = {
val addrWidth = widthOf(addr)
(for(bitId <- 0 until resultWidth) yield{
val trueTerm = mapping.filter { case (k,t) => (t.care.testBit(bitId) && t.value.testBit(bitId))}.map(_._1)
val falseTerm = mapping.filter { case (k,t) => (t.care.testBit(bitId) && !t.value.testBit(bitId))}.map(_._1)
val symplifiedTerms = SymplifyBit.getPrimeImplicants(trueTerm.toSeq, falseTerm.toSeq, addrWidth)
logicOf(addr, symplifiedTerms)
}).asBits
}
}
object SymplifyBit{
def genImplicitDontCare(falseTerms: Seq[Masked], term: Masked, bits: Int, above: Boolean): Masked = {
for (i <- 0 until bits; if term.care.testBit(i)) {
var t: Masked = null
if(above) {
if (!term.value.testBit(i))
t = Masked(term.value.setBit(i), term.care)
} else {
if (term.value.testBit(i))
t = Masked(term.value.clearBit(i), term.care)
}
if (t != null && !falseTerms.exists(_.intersects(t)))
return t
}
null
}
def getPrimeImplicants(trueTerms: Seq[Masked],falseTerms: Seq[Masked],inputWidth : Int): Seq[Masked] = {
val primes = ArrayBuffer[Masked]()
trueTerms.foreach(_.isPrime = true)
falseTerms.foreach(_.isPrime = true)
val trueTermByCareCount = (inputWidth to 0 by -1).map(b => trueTerms.filter(b == _.care.bitCount))
val table = trueTermByCareCount.map(c => (0 to inputWidth).map(b => collection.mutable.Set(c.filter(b == _.value.bitCount): _*)))
for (i <- 0 to inputWidth) {
for (j <- 0 until inputWidth - i){
for(term <- table(i)(j)){
table(i+1)(j) ++= table(i)(j+1).filter(_.similar(term)).map(_.merge(term))
}
}
for (j <- 0 until inputWidth-i) {
for (a <- table(i)(j).filter(_.isPrime)) {
val dc = genImplicitDontCare(falseTerms, a, inputWidth, true)
if (dc != null)
table(i+1)(j) += dc merge a
}
for (a <- table(i)(j+1).filter(_.isPrime)) {
val dc = genImplicitDontCare(falseTerms, a, inputWidth, false)
if (dc != null)
table(i+1)(j) += a merge dc
}
}
for (r <- table(i))
for (p <- r; if p.isPrime)
primes += p
}
primes
}
def getPrimeImplicants(trueTerms: Seq[Masked],inputWidth : Int): Seq[Masked] = {
val primes = ArrayBuffer[Masked]()
trueTerms.foreach(_.isPrime = true)
val trueTermByCareCount = (inputWidth to 0 by -1).map(b => trueTerms.filter(b == _.care.bitCount))
val table = trueTermByCareCount.map(c => (0 to inputWidth).map(b => collection.mutable.Set(c.filter(b == _.value.bitCount): _*)))
for (i <- 0 to inputWidth) {
for (j <- 0 until inputWidth - i){
for(term <- table(i)(j)){
table(i+1)(j) ++= table(i)(j+1).filter(_.similar(term)).map(_.merge(term))
}
}
for (r <- table(i))
for (p <- r; if p.isPrime)
primes += p
}
primes
}
def main(args: Array[String]) {
val default = Masked(0,0xF)
val primeImplicants = List(4,8,10,11,12,15).map(v => Masked(v,0xF))
val dcImplicants = List(9,14).map(v => Masked(v,0xF).setPrime(false))
val reducedPrimeImplicants = getPrimeImplicants(primeImplicants ++ dcImplicants,4)
println("UUT")
println(reducedPrimeImplicants.map(_.toString(4)).mkString("\n"))
println("REF")
println("-100\n10--\n1--0\n1-1-")
}
}

1
src/main/scala/SpinalRiscv/Plugin/DivPlugin.scala
View File

@ -12,7 +12,6 @@ class DivPlugin extends Plugin[VexRiscv]{
import pipeline.config._
val actions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.RS,
REGFILE_WRITE_VALID -> True,

3
src/main/scala/SpinalRiscv/Plugin/IntAluPlugin.scala
View File

@ -19,7 +19,6 @@ class IntAluPlugin extends Plugin[VexRiscv]{
import pipeline.config._
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.IMI,
REGFILE_WRITE_VALID -> True,
@ -29,7 +28,6 @@ class IntAluPlugin extends Plugin[VexRiscv]{
)
val nonImmediateActions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.RS,
REGFILE_WRITE_VALID -> True,
@ -40,7 +38,6 @@ class IntAluPlugin extends Plugin[VexRiscv]{
)
val otherAction = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
REGFILE_WRITE_VALID -> True,
BYPASSABLE_EXECUTE_STAGE -> True,
BYPASSABLE_MEMORY_STAGE -> True

2
src/main/scala/SpinalRiscv/Plugin/MachineCsr.scala
View File

@ -95,11 +95,9 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
import pipeline.config._
val defaultEnv = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True
)
val defaultCsrActions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
IS_CSR -> True,
REGFILE_WRITE_VALID -> True,
BYPASSABLE_EXECUTE_STAGE -> False,

1
src/main/scala/SpinalRiscv/Plugin/MulPlugin.scala
View File

@ -19,7 +19,6 @@ class MulPlugin extends Plugin[VexRiscv]{
val actions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.RS,
REGFILE_WRITE_VALID -> True,

4
src/main/scala/SpinalRiscv/Plugin/ShiftPlugins.scala
View File

@ -21,7 +21,6 @@ class FullBarrielShifterPlugin extends Plugin[VexRiscv]{
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.IMI,
REGFILE_WRITE_VALID -> True,
@ -31,7 +30,6 @@ class FullBarrielShifterPlugin extends Plugin[VexRiscv]{
)
val nonImmediateActions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.RS,
REGFILE_WRITE_VALID -> True,
@ -97,7 +95,6 @@ class LightShifterPlugin extends Plugin[VexRiscv]{
val immediateActions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.IMI,
ALU_CTRL -> AluCtrlEnum.SRC1,
@ -108,7 +105,6 @@ class LightShifterPlugin extends Plugin[VexRiscv]{
)
val nonImmediateActions = List[(Stageable[_ <: BaseType],Any)](
LEGAL_INSTRUCTION -> True,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.RS,
ALU_CTRL -> AluCtrlEnum.SRC1,

56
src/main/scala/SpinalRiscv/TopLevel.scala
View File

@ -79,37 +79,37 @@ object TopLevel {
config.plugins ++= List(
new PcManagerSimplePlugin(0x00000000l, false),
// new IBusSimplePlugin(
// interfaceKeepData = true,
// catchAccessFault = true
// ),
new IBusCachedPlugin(
config = InstructionCacheConfig(
cacheSize =4096,
bytePerLine =32,
wayCount = 1,
wrappedMemAccess = true,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchAccessFault = true
)
new IBusSimplePlugin(
interfaceKeepData = true,
catchAccessFault = true
),
// new DBusSimplePlugin(
// catchAddressMisaligned = true,
// catchAccessFault = true
// new IBusCachedPlugin(
// config = InstructionCacheConfig(
// cacheSize =4096,
// bytePerLine =32,
// wayCount = 1,
// wrappedMemAccess = true,
// addressWidth = 32,
// cpuDataWidth = 32,
// memDataWidth = 32,
// catchAccessFault = true
// )
// ),
new DBusCachedPlugin(
config = new DataCacheConfig(
cacheSize = 4096,
bytePerLine = 32,
wayCount = 1,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchAccessFault = false
)
new DBusSimplePlugin(
catchAddressMisaligned = true,
catchAccessFault = true
),
// new DBusCachedPlugin(
// config = new DataCacheConfig(
// cacheSize = 4096,
// bytePerLine = 32,
// wayCount = 1,
// addressWidth = 32,
// cpuDataWidth = 32,
// memDataWidth = 32,
// catchAccessFault = false
// )
// ),
new DecoderSimplePlugin(
catchIllegalInstruction = true
),

120
src/test/cpp/testA/fail.gtkw
View File

@ -1,130 +1,42 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Sat Apr 1 14:47:34 2017
[*] Sat Apr 1 15:43:19 2017
[*]
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/dhrystoneO3.vcd"
[dumpfile_mtime] "Sat Apr 1 14:46:24 2017"
[dumpfile_size] 1846070138
[dumpfile_mtime] "Sat Apr 1 15:42:10 2017"
[dumpfile_size] 214475745
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/fail.gtkw"
[timestart] 48127
[timestart] 0
[size] 1776 953
[pos] -1 -1
*-3.000000 48140 48755 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-16.000000 553 48755 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.VexRiscv.
[sst_width] 313
[signals_width] 558
[sst_expanded] 1
[sst_vpaned_height] 374
[sst_vpaned_height] 593
@28
TOP.clk
TOP.reset
@22
TOP.dBus_cmd_payload_address[31:0]
TOP.dBus_cmd_payload_data[31:0]
TOP.dBus_cmd_payload_length[3:0]
TOP.dBus_cmd_payload_mask[3:0]
@28
TOP.dBus_cmd_payload_wr
TOP.dBus_cmd_ready
TOP.dBus_cmd_valid
@22
TOP.dBus_rsp_payload_data[31:0]
@28
TOP.dBus_rsp_valid
TOP.VexRiscv.dataCache_1.victim_bufferReaded_valid
TOP.VexRiscv.dataCache_1.io_cpu_execute_isValid
TOP.VexRiscv.dataCache_1.io_cpu_memory_isValid
TOP.VexRiscv.dataCache_1.loader_valid
TOP.VexRiscv.writeBack_arbitration_isValid
@22
TOP.VexRiscv.dataCache_1.io_cpu_writeBack_data[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_writeBack_haltIt
TOP.VexRiscv.dataCache_1.io_cpu_memory_haltIt
TOP.VexRiscv.dataCache_1.io_cpu_memory_isStuck
TOP.VexRiscv.dataCache_1.io_cpu_memory_isValid
TOP.VexRiscv.dataCache_1.manager_cpuRsp_payload_fromBypass
TOP.VexRiscv.dataCache_1.manager_cpuRsp_ready
TOP.VexRiscv.dataCache_1.manager_cpuRsp_valid
@22
TOP.VexRiscv.dataCache_1.ways_0_data_port0_address[9:0]
TOP.VexRiscv.dataCache_1.ways_0_data_port0_data[31:0]
@28
TOP.VexRiscv.dataCache_1.ways_0_data_port0_enable
@22
TOP.VexRiscv.dataCache_1.ways_0_data_port0_mask[3:0]
TOP.VexRiscv.dataCache_1.ways_0_data_port1_address[9:0]
TOP.VexRiscv.dataCache_1.ways_0_data_port1_data[31:0]
@28
TOP.VexRiscv.dataCache_1.ways_0_data_port1_enable
@22
TOP.VexRiscv.dataCache_1.dataReadedValue_0[31:0]
@28
TOP.VexRiscv.dataCache_1.manager_cpuRsp_payload_fromBypass
TOP.VexRiscv.dataCache_1.manager_cpuRsp_ready
TOP.VexRiscv.dataCache_1.manager_cpuRsp_valid
TOP.VexRiscv.writeBack_REGFILE_WRITE_VALID
@22
TOP.VexRiscv.writeBack_REGFILE_WRITE_DATA[31:0]
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0]
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0]
@28
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_valid
@800200
-cache_mem
@23
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_address[31:0]
@22
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_data[31:0]
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_length[3:0]
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_mask[3:0]
@28
TOP.VexRiscv.dataCache_1.io_mem_cmd_payload_wr
TOP.VexRiscv.dataCache_1.io_mem_cmd_valid
TOP.VexRiscv.dataCache_1.io_mem_cmd_ready
@22
TOP.VexRiscv.dataCache_1.io_mem_rsp_payload_data[31:0]
@28
TOP.VexRiscv.dataCache_1.io_mem_rsp_valid
@1000200
-cache_mem
@28
TOP.VexRiscv.clk
@22
TOP.VexRiscv.writeBack_PC[31:0]
TOP.VexRiscv.dataCache_1.io_cpu_writeBack_data[31:0]
@28
TOP.VexRiscv.writeBack_arbitration_isValid
TOP.VexRiscv.decode_arbitration_haltIt
TOP.VexRiscv.execute_arbitration_haltIt
TOP.VexRiscv.fetch_arbitration_haltIt
TOP.VexRiscv.memory_arbitration_haltIt
TOP.VexRiscv.prefetch_arbitration_haltIt
TOP.VexRiscv.writeBack_arbitration_haltIt
TOP.VexRiscv.MachineCsr_exceptionPortCtrl_pipelineHasException
@800200
-cache_cpu
TOP.VexRiscv.writeBack_MEMORY_ENABLE
TOP.VexRiscv.writeBack_arbitration_isFiring
TOP.VexRiscv.dataCache_1.ways_0_data_port0_enable
@22
TOP.VexRiscv.execute_PC[31:0]
TOP.VexRiscv.dataCache_1.ways_0_data_port0_data[31:0]
@28
TOP.VexRiscv.execute_arbitration_removeIt
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_address[31:0]
TOP.VexRiscv.dataCache_1.manager_cpuRspIn_ready
@29
TOP.VexRiscv.dataCache_1.manager_cpuRspIn_valid
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_all
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_bypass
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_data[31:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_kind[1:0]
@22
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_mask[3:0]
@28
TOP.VexRiscv.dataCache_1.io_cpu_execute_args_wr
TOP.VexRiscv.dataCache_1.io_cpu_execute_haltIt
TOP.VexRiscv.dataCache_1.io_cpu_execute_isStuck
TOP.VexRiscv.dataCache_1.io_cpu_execute_isValid
@1000200
-cache_cpu
TOP.VexRiscv.dataCache_1.manager_cpuRsp_ready
TOP.VexRiscv.dataCache_1.manager_cpuRsp_valid
[pattern_trace] 1
[pattern_trace] 0

4
src/test/cpp/testA/makefile
View File

@ -1,5 +1,5 @@
IBUS=IBUS_CACHED
DBUS=DBUS_CACHED
IBUS=IBUS_SIMPLE
DBUS=DBUS_SIMPLE
TRACE=no
TRACE_START=0
CSR=yes