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VexRiscv
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Add wfiGenAsWait and wfiGenAsNop 

CsrPlugin cleaning
Much cleaning in general
Zephyr is running
This commit is contained in:
Dolu1990 2018-10-16 13:07:30 +02:00
parent f903df4b66
commit 905abd5aaa
21 changed files with 188 additions and 48 deletions
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34
src/main/scala/vexriscv/TestsWorkspace.scala
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@ -35,10 +35,10 @@ object TestsWorkspace {
resetVector = 0x80000000l,
cmdForkOnSecondStage = false,
cmdForkPersistence = false,
prediction = STATIC,
prediction = NONE,
historyRamSizeLog2 = 10,
catchAccessFault = true,
compressedGen = true,
catchAccessFault = false,
compressedGen = false,
busLatencyMin = 1,
injectorStage = true
),
@ -67,7 +67,7 @@ object TestsWorkspace {
// ),
new DBusSimplePlugin(
catchAddressMisaligned = true,
catchAccessFault = true,
catchAccessFault = false,
earlyInjection = false
),
// new DBusCachedPlugin(
@ -98,7 +98,7 @@ object TestsWorkspace {
ioRange = _(31 downto 28) === 0xF
),
new DecoderSimplePlugin(
catchIllegalInstruction = true
catchIllegalInstruction = false
),
new RegFilePlugin(
regFileReadyKind = plugin.ASYNC,
@ -129,7 +129,29 @@ object TestsWorkspace {
divUnrollFactor = 1
),
// new DivPlugin,
new CsrPlugin(CsrPluginConfig.all2(0x80000020l).copy(deterministicInteruptionEntry = false, ebreakGen = true)),
new CsrPlugin(//CsrPluginConfig.all2(0x80000020l).copy(ebreakGen = true)/*
CsrPluginConfig(
catchIllegalAccess = false,
mvendorid = null,
marchid = null,
mimpid = null,
mhartid = null,
misaExtensionsInit = 0,
misaAccess = CsrAccess.READ_ONLY,
mtvecAccess = CsrAccess.WRITE_ONLY,
mtvecInit = 0x80000020l,
mepcAccess = CsrAccess.READ_WRITE,
mscratchGen = true,
mcauseAccess = CsrAccess.READ_ONLY,
mbadaddrAccess = CsrAccess.READ_ONLY,
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ecallGen = true,
ebreakGen = true,
wfiGenAsWait = false,
wfiGenAsNop = true,
ucycleAccess = CsrAccess.NONE
)),
// new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
new BranchPlugin(
earlyBranch = true,

2
src/main/scala/vexriscv/demo/Briey.scala
View File

@ -146,7 +146,7 @@ object BrieyConfig{
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
)
),

4
src/main/scala/vexriscv/demo/GenFull.scala
View File

@ -12,10 +12,6 @@ object GenFull extends App{
def cpu() = new VexRiscv(
config = VexRiscvConfig(
plugins = List(
new PcManagerSimplePlugin(
resetVector = 0x80000000l,
relaxedPcCalculation = false
),
new IBusCachedPlugin(
prediction = DYNAMIC,
config = InstructionCacheConfig(

2
src/main/scala/vexriscv/demo/Murax.scala
View File

@ -80,7 +80,7 @@ object MuraxConfig{
catchAccessFault = false,
earlyInjection = false
),
new CsrPlugin(CsrPluginConfig.smallest(mtvecInit = if(withXip) 0xE0040020l else 0x80000000l)),
new CsrPlugin(CsrPluginConfig.smallest(mtvecInit = if(withXip) 0xE0040020l else 0x80000020l)),
new DecoderSimplePlugin(
catchIllegalInstruction = false
),

5
src/main/scala/vexriscv/demo/MuraxUtiles.scala
View File

@ -31,6 +31,11 @@ case class SimpleBus(config : SimpleBusConfig) extends Bundle with IMasterSlave
master(cmd)
slave(rsp)
}
def resizableAddress() : this.type = {
cmd.address.addTag(tagAutoResize)
this
}
}
class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{

2
src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
View File

@ -125,7 +125,7 @@ object VexRiscvAvalonForSim{
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
)
),

2
src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
View File

@ -122,7 +122,7 @@ object VexRiscvAvalonWithIntegratedJtag{
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
)
),

2
src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
View File

@ -123,7 +123,7 @@ object VexRiscvAxi4WithIntegratedJtag{
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
)
),

25
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -49,8 +49,10 @@ case class CsrPluginConfig(
mcycleAccess : CsrAccess,
minstretAccess : CsrAccess,
ucycleAccess : CsrAccess,
wfiGen : Boolean,
wfiGenAsWait : Boolean,
ecallGen : Boolean,
noCsrAlu : Boolean = false,
wfiGenAsNop : Boolean = false,
ebreakGen : Boolean = false,
supervisorGen : Boolean = false,
sscratchGen : Boolean = false,
@ -92,7 +94,7 @@ object CsrPluginConfig{
mcycleAccess = CsrAccess.READ_WRITE,
minstretAccess = CsrAccess.READ_WRITE,
ecallGen = true,
wfiGen = true,
wfiGenAsWait = true,
ucycleAccess = CsrAccess.READ_ONLY
)
@ -113,7 +115,7 @@ object CsrPluginConfig{
mcycleAccess = CsrAccess.READ_WRITE,
minstretAccess = CsrAccess.READ_WRITE,
ecallGen = true,
wfiGen = true,
wfiGenAsWait = true,
ucycleAccess = CsrAccess.READ_ONLY,
supervisorGen = true,
sscratchGen = true,
@ -145,7 +147,7 @@ object CsrPluginConfig{
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
)
@ -166,7 +168,7 @@ object CsrPluginConfig{
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
)
@ -226,6 +228,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
import config._
import CsrAccess._
assert(!(wfiGenAsNop && wfiGenAsWait))
def xlen = 32
//Mannage ExceptionService calls
@ -247,7 +251,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
object EnvCtrlEnum extends SpinalEnum(binarySequential){
val NONE, XRET = newElement()
val WFI = if(wfiGen) newElement() else null
val WFI = if(wfiGenAsWait) newElement() else null
val ECALL = if(ecallGen) newElement() else null
val EBREAK = if(ebreakGen) newElement() else null
}
@ -304,7 +308,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
MRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.XRET, HAS_SIDE_EFFECT -> True)),
SRET -> (defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.XRET, HAS_SIDE_EFFECT -> True))
))
if(wfiGen) decoderService.add(WFI, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.WFI))
if(wfiGenAsWait) decoderService.add(WFI, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.WFI))
if(wfiGenAsNop) decoderService.add(WFI, Nil)
if(ecallGen) decoderService.add(ECALL, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.ECALL, HAS_SIDE_EFFECT -> True))
if(ebreakGen) decoderService.add(EBREAK, defaultEnv ++ List(ENV_CTRL -> EnvCtrlEnum.EBREAK, HAS_SIDE_EFFECT -> True))
@ -611,7 +616,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
interrupt.clearWhen(!allowInterrupts)
val exception = if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionValids.last && allowException else False
val writeBackWasWfi = if(wfiGen) RegNext(writeBack.arbitration.isFiring && writeBack.input(ENV_CTRL) === EnvCtrlEnum.WFI) init(False) else False
val writeBackWasWfi = if(wfiGenAsWait) RegNext(writeBack.arbitration.isFiring && writeBack.input(ENV_CTRL) === EnvCtrlEnum.WFI) init(False) else False
@ -727,7 +732,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
execute plug new Area{
import execute._
//Manage WFI instructions
if(wfiGen) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){
if(wfiGenAsWait) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){
when(!interrupt){
arbitration.haltItself := True
}
@ -776,7 +781,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
val readData = B(0, 32 bits)
// def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT
// val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck)
val writeData = input(INSTRUCTION)(13).mux(
val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux(
False -> writeSrc,
True -> Mux(input(INSTRUCTION)(12), readData & ~writeSrc, readData | writeSrc)
)

6
src/main/scala/vexriscv/plugin/Fetcher.scala
View File

@ -11,8 +11,7 @@ import scala.collection.mutable.ArrayBuffer
//TODO val killLastStage = jump.pcLoad.valid || decode.arbitration.isRemoved
// DBUSSimple check memory halt execute optimization
abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
val resetVector : BigInt,
abstract class IBusFetcherImpl(val resetVector : BigInt,
val keepPcPlus4 : Boolean,
val decodePcGen : Boolean,
val compressedGen : Boolean,
@ -62,9 +61,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
fetcherHalt = False
fetcherflushIt = False
incomingInstruction = False
if(catchAccessFault) {
val exceptionService = pipeline.service(classOf[ExceptionService])
}
if(resetVector == null) externalResetVector = in(UInt(32 bits).setName("externalResetVector"))
pipeline(RVC_GEN) = compressedGen

1
src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
View File

@ -18,7 +18,6 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
config : InstructionCacheConfig,
memoryTranslatorPortConfig : Any = null,
injectorStage : Boolean = false) extends IBusFetcherImpl(
catchAccessFault = config.catchAccessFault,
resetVector = resetVector,
keepPcPlus4 = keepPcPlus4,
decodePcGen = compressedGen,

3
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View File

@ -62,7 +62,7 @@ object IBusSimpleBus{
}
case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMasterSlave {
case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle with IMasterSlave {
var cmd = Stream(IBusSimpleCmd())
var rsp = Flow(IBusSimpleRsp())
@ -155,7 +155,6 @@ class IBusSimplePlugin(resetVector : BigInt,
injectorStage : Boolean = true,
rspHoldValue : Boolean = false
) extends IBusFetcherImpl(
catchAccessFault = catchAccessFault,
resetVector = resetVector,
keepPcPlus4 = keepPcPlus4,
decodePcGen = compressedGen,

1
src/main/scala/vexriscv/plugin/RegFilePlugin.scala
View File

@ -81,5 +81,6 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,
inputInit[Bits](REGFILE_WRITE_DATA, 0)
inputInit[Bits](INSTRUCTION, 0)
}
}
}

2
src/test/cpp/regression/.cproject
View File

@ -18,7 +18,7 @@
<folderInfo id="cdt.managedbuild.toolchain.gnu.base.980376357.1040916561" name="/" resourcePath="">
<toolChain id="cdt.managedbuild.toolchain.gnu.base.1338997315" name="cdt.managedbuild.toolchain.gnu.base" superClass="cdt.managedbuild.toolchain.gnu.base">
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="cdt.managedbuild.target.gnu.platform.base.2110298829" name="Debug Platform" osList="linux,hpux,aix,qnx" superClass="cdt.managedbuild.target.gnu.platform.base"/>
<builder arguments="compile MMU=no IBUS=SIMPLE DBUS=SIMPLE REDO=1 TRACE=yes TRACE_ACCESS=yes DEBUG=yes" command="make" id="cdt.managedbuild.target.gnu.builder.base.1143542178" incrementalBuildTarget="compile" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="cdt.managedbuild.target.gnu.builder.base"/>
<builder arguments="compile IBUS=SIMPLE DBUS=SIMPLE MMU=no DEBUG_PLUGIN=no COMPRESSED=yes REDO=0 DHRYSTONE=no FREERTOS=4 DEBUG=yes" command="make" id="cdt.managedbuild.target.gnu.builder.base.1143542178" incrementalBuildTarget="compile" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="cdt.managedbuild.target.gnu.builder.base"/>
<tool id="cdt.managedbuild.tool.gnu.archiver.base.2117481176" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.base.1759629739" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.base">
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1789548329" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>

1
src/test/cpp/regression/.gitignore vendored
View File

@ -1,2 +1,3 @@
*.regTraceRef
/freertos.gtkw
*.cproject

56
src/test/cpp/regression/main.cpp
View File

@ -301,6 +301,7 @@ public:
status.mpie = status.mie;
mepc = pc;
pcWrite(mtvec.base << 2);
if(interrupt) livenessInterrupt = 0;
//status.MPP := privilege
}
@ -333,7 +334,35 @@ public:
*csrPtr(csr) = value;
}
int livenessStep = 0;
int livenessInterrupt = 0;
virtual void liveness(bool mIntTimer, bool mIntExt){
livenessStep++;
bool interruptRequest = (mie.mtie && mIntTimer);
if(interruptRequest){
if(status.mie){
livenessInterrupt++;
}
} else {
livenessInterrupt = 0;
}
if(livenessStep > 1000){
cout << "Liveness step failure" << endl;
fail();
}
if(livenessInterrupt > 1000){
cout << "Liveness interrupt failure" << endl;
fail();
}
}
virtual void step() {
livenessStep = 0;
#define rd32 ((i >> 7) & 0x1F)
#define iBits(lo, len) ((i >> lo) & ((1 << len)-1))
#define iBitsSigned(lo, len) int32_t(i) << (32-lo-len) >> (32-len)
@ -970,7 +999,7 @@ public:
mTime += top->VexRiscv->writeBack_arbitration_isFiring*MTIME_INSTR_FACTOR;
#endif
#endif
#ifdef CSR
#ifdef TIMER_INTERRUPT
top->timerInterrupt = mTime >= mTimeCmp ? 1 : 0;
//if(mTime == mTimeCmp) printf("SIM timer tick\n");
#endif
@ -998,7 +1027,21 @@ public:
fail();
}
if(riscvRefEnable) riscvRef.step();
if(riscvRefEnable) {
riscvRef.step();
bool mIntTimer = false;
bool mIntExt = false;
#ifdef TIMER_INTERRUPT
mIntTimer = top->timerInterrupt;
#endif
#ifdef EXTERNAL_INTERRUPT
mIntExt = top->externalInterrupt;
#endif
riscvRef.liveness(mIntTimer, mIntExt);
}
@ -2576,10 +2619,13 @@ int main(int argc, char **argv, char **env) {
for(int idx = 0;idx < 1;idx++){
#ifdef DEBUG_PLUGIN_EXTERNAL
#if defined(DEBUG_PLUGIN_EXTERNAL) || defined(RUN_HEX)
{
Workspace w("debugPluginExternal");
w.loadHex("../../resources/hex/debugPluginExternal.hex");
Workspace w("run");
#ifdef RUN_HEX
//w.loadHex("/home/spinalvm/hdl/zephyr/zephyrSpinalHdl/samples/synchronization/build/zephyr/zephyr.hex");
w.loadHex(RUN_HEX);
#endif
w.noInstructionReadCheck();
//w.setIStall(false);
//w.setDStall(false);

13
src/test/cpp/regression/makefile
View File

@ -17,6 +17,7 @@ ATOMIC?=no
NO_STALL?=no
DEBUG_PLUGIN?=STD
DEBUG_PLUGIN_EXTERNAL?=no
RUN_HEX=no
CUSTOM_SIMD_ADD?=no
CUSTOM_CSR?=no
DHRYSTONE=yes
@ -42,7 +43,19 @@ ifeq ($(DEBUG),yes)
ADDCFLAGS += -CFLAGS -O0 -CFLAGS -g
else
ADDCFLAGS += -CFLAGS -O3
endif
ifneq ($(shell dplus -VV | grep timerInterrupt ../../../../VexRiscv.v -w),)
ADDCFLAGS += -CFLAGS -DTIMER_INTERRUPT
endif
ifneq ($(shell dplus -VV | grep externalInterrupt ../../../../VexRiscv.v -w),)
ADDCFLAGS += -CFLAGS -DEXTERNAL_INTERRUPT
endif
ifneq ($(RUN_HEX),no)
ADDCFLAGS += -CFLAGS -DRUN_HEX='\"$(RUN_HEX)\"'
endif
ifeq ($(COMPRESSED),yes)

2
src/test/python/gcloud/remoteTest.py
View File

@ -14,6 +14,8 @@ gci.stopScript("src/test/python/gcloud/stopScript.sh")
gci.local("rm -rf archive.tar.gz; git ls-files -z | xargs -0 tar -czf archive.tar.gz")
gci.localToRemote("archive.tar.gz", "")
gci.local("cd ../SpinalHDL; rm -rf spinal.tar.gz; git ls-files -z | xargs -0 tar -czf spinal.tar.gz")
gci.localToRemote("../SpinalHDL/spinal.tar.gz", "")
gci.localToRemote("src/test/python/gcloud/run.sh", "")
gci.remote("rm -rf run.txt; setsid nohup sh run.sh &> run.txt")

8
src/test/python/gcloud/run.sh
View File

@ -1,9 +1,15 @@
rm -rf sbtTest.txt
rm -rf VexRiscv
rm -rf SpinalHDL
#git clone https://github.com/SpinalHDL/SpinalHDL.git -b dev
mkdir SpinalHDL
tar -xzf spinal.tar.gz -C SpinalHDL
mkdir VexRiscv
tar -xzf archive.tar.gz -C VexRiscv
cd VexRiscv
sudo git init
sudo git add *
sudo git commit -m miaou
export VEXRISCV_REGRESSION_CONFIG_COUNT=16
export VEXRISCV_REGRESSION_FREERTOS_COUNT=yes
sbt test

4
src/test/scala/vexriscv/TestIndividualFeatures.scala
View File

@ -523,8 +523,8 @@ class TestIndividualFeatures extends FunSuite {
// val testId = Some(mutable.HashSet[Int](0,28,45,93))
// val testId = Some(mutable.HashSet[Int](0))
// val seed = 2094440864560126345l
// val testId = Some(mutable.HashSet[Int](9))
// val seed = -8173808854505304814l

59
src/test/scala/vexriscv/experimental/GenMicro.scala
View File

@ -13,12 +13,14 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
object GenMicro extends App{
def cpu() = {
val removeOneFetchStage = true
val pessimisticHazard = true
val writeBackOpt = true
val onlyLoadWords = false
val rspHoldValue = true
val withCompliantCsr = true
val withCompliantCsrPlusEmulation = true
val earlyBranch = false
val noShifter = false
val pessimisticHazard = true
val onlyLoadWords = false
new VexRiscv(
config = VexRiscvConfig(
plugins = List(
@ -38,13 +40,13 @@ object GenMicro extends App{
rspHoldValue = rspHoldValue
),
new DBusSimplePlugin(
catchAddressMisaligned = false,
catchAddressMisaligned = withCompliantCsr,
catchAccessFault = false,
earlyInjection = writeBackOpt,
onlyLoadWords = onlyLoadWords
),
new DecoderSimplePlugin(
catchIllegalInstruction = false
catchIllegalInstruction = withCompliantCsrPlusEmulation
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
@ -71,10 +73,57 @@ object GenMicro extends App{
new HazardPessimisticPlugin(),
new BranchPlugin(
earlyBranch = earlyBranch,
catchAddressMisaligned = false
catchAddressMisaligned = withCompliantCsr,
fenceiGenAsAJump = withCompliantCsr
),
new YamlPlugin("cpu0.yaml")
) ++ (if(noShifter) Nil else List(new LightShifterPlugin))
++ (if(!withCompliantCsr) Nil else List(new CsrPlugin(
config = if(withCompliantCsrPlusEmulation)CsrPluginConfig(
catchIllegalAccess = true,
mvendorid = null,
marchid = null,
mimpid = null,
mhartid = null,
misaExtensionsInit = 0,
misaAccess = CsrAccess.NONE,
mtvecAccess = CsrAccess.NONE,
mtvecInit = 0x80000020l,
mepcAccess = CsrAccess.NONE,
mscratchGen = false,
mcauseAccess = CsrAccess.READ_ONLY,
mbadaddrAccess = CsrAccess.NONE,
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ecallGen = false,
ebreakGen = false,
wfiGenAsWait = false,
wfiGenAsNop = false,
ucycleAccess = CsrAccess.NONE,
noCsrAlu = true
) else CsrPluginConfig(
catchIllegalAccess = false,
mvendorid = null,
marchid = null,
mimpid = null,
mhartid = null,
misaExtensionsInit = 0,
misaAccess = CsrAccess.READ_ONLY,
mtvecAccess = CsrAccess.WRITE_ONLY,
mtvecInit = 0x80000020l,
mepcAccess = CsrAccess.READ_WRITE,
mscratchGen = true,
mcauseAccess = CsrAccess.READ_ONLY,
mbadaddrAccess = CsrAccess.READ_ONLY,
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ecallGen = true,
ebreakGen = true,
wfiGenAsWait = false,
wfiGenAsNop = true,
ucycleAccess = CsrAccess.NONE
)
)))
)
)
}