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VexRiscv
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Merge remote-tracking branch 'origin/master' into dev

This commit is contained in:
Dolu1990 2018-12-30 15:53:25 +01:00
parent 92065a1a10 d617bafb08
commit 927ab6d127
1 changed files with 40 additions and 39 deletions
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79
src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
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@ -26,7 +26,7 @@ object VexRiscvAvalonForSim{
//CPU configuration //CPU configuration
val cpuConfig = VexRiscvConfig( val cpuConfig = VexRiscvConfig(
plugins = List( plugins = List(
new IBusSimplePlugin( /* new IBusSimplePlugin(
resetVector = 0x00000000l, resetVector = 0x00000000l,
cmdForkOnSecondStage = false, cmdForkOnSecondStage = false,
cmdForkPersistence = false, cmdForkPersistence = false,
@ -37,44 +37,44 @@ object VexRiscvAvalonForSim{
new DBusSimplePlugin( new DBusSimplePlugin(
catchAddressMisaligned = false, catchAddressMisaligned = false,
catchAccessFault = false catchAccessFault = false
),*/
new IBusCachedPlugin(
config = InstructionCacheConfig(
cacheSize = 4096,
bytePerLine =32,
wayCount = 1,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchIllegalAccess = true,
catchAccessFault = true,
catchMemoryTranslationMiss = true,
asyncTagMemory = false,
twoCycleRam = true
)
// askMemoryTranslation = true,
// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
// portTlbSize = 4
// )
),
new DBusCachedPlugin(
config = new DataCacheConfig(
cacheSize = 4096,
bytePerLine = 32,
wayCount = 1,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchAccessError = true,
catchIllegal = true,
catchUnaligned = true,
catchMemoryTranslationMiss = true
),
memoryTranslatorPortConfig = null
// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
// portTlbSize = 6
// )
), ),
// new IBusCachedPlugin(
// config = InstructionCacheConfig(
// cacheSize = 4096,
// bytePerLine =32,
// wayCount = 1,
// addressWidth = 32,
// cpuDataWidth = 32,
// memDataWidth = 32,
// catchIllegalAccess = true,
// catchAccessFault = true,
// catchMemoryTranslationMiss = true,
// asyncTagMemory = false,
// twoCycleRam = true
// )
// // askMemoryTranslation = true,
// // memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
// // portTlbSize = 4
// // )
// ),
// new DBusCachedPlugin(
// config = new DataCacheConfig(
// cacheSize = 4096,
// bytePerLine = 32,
// wayCount = 1,
// addressWidth = 32,
// cpuDataWidth = 32,
// memDataWidth = 32,
// catchAccessError = true,
// catchIllegal = true,
// catchUnaligned = true,
// catchMemoryTranslationMiss = true
// ),
// memoryTranslatorPortConfig = null
// // memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
// // portTlbSize = 6
// // )
// ),
new StaticMemoryTranslatorPlugin( new StaticMemoryTranslatorPlugin(
ioRange = _(31 downto 28) === 0xF ioRange = _(31 downto 28) === 0xF
), ),
@ -165,7 +165,7 @@ object VexRiscvAvalonForSim{
.setName("dBusAvalon") .setName("dBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) .addTag(ClockDomainTag(ClockDomain.current))
} }
case plugin: DebugPlugin => { case plugin: DebugPlugin => plugin.debugClockDomain {
plugin.io.bus.setAsDirectionLess() plugin.io.bus.setAsDirectionLess()
slave(plugin.io.bus.fromAvalon()) slave(plugin.io.bus.fromAvalon())
.setName("debugBusAvalon") .setName("debugBusAvalon")
@ -194,3 +194,4 @@ object VexRiscvAvalonForSim{
QSysify(report.toplevel) QSysify(report.toplevel)
} }
} }