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VexRiscv
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Add cache bandwidth counter

This commit is contained in:
Charles Papon 2019-05-25 00:21:48 +02:00
parent 206c7ca638
commit 94606d38e2
1 changed files with 1 additions and 1 deletions
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src/main/scala/vexriscv/ip/InstructionCache.scala
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@ -362,7 +362,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
io.mem.cmd.address := address(tagRange.high downto lineRange.low) @@ U(0,lineRange.low bit)
io.mem.cmd.size := log2Up(p.bytePerLine)
val wayToAllocate = Counter(wayCount, fire)
val wayToAllocate = Counter(wayCount, !valid)
val wordIndex = Reg(UInt(log2Up(memWordPerLine) bits)) init(0)