Add instruction cache plugin (tested)
This commit is contained in:
Charles Papon
parent
32d32845bd
commit
95585b4d9a
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@ -0,0 +1,318 @@
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package SpinalRiscv.Plugin
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import SpinalRiscv._
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import spinal.core._
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import spinal.lib._
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case class InstructionCacheConfig( cacheSize : Int,
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bytePerLine : Int,
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wayCount : Int,
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wrappedMemAccess : Boolean,
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addressWidth : Int,
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cpuDataWidth : Int,
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memDataWidth : Int){
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def burstSize = bytePerLine*8/memDataWidth
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}
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class IBusCachedPlugin(catchAccessFault : Boolean, cacheConfig : InstructionCacheConfig) extends Plugin[VexRiscv]{
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var iBus : InstructionCacheMemBus = null
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object IBUS_ACCESS_ERROR extends Stageable(Bool)
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var decodeExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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pipeline.unremovableStages += pipeline.prefetch
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if(catchAccessFault) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1)
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}
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}
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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assert(catchAccessFault == false) //unimplemented
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val cache = new InstructionCache(cacheConfig)
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iBus = master(new InstructionCacheMemBus(cacheConfig)).setName("iBus")
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iBus <> cache.io.mem
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//Connect prefetch cache side
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cache.io.cpu.cmd.isValid := prefetch.arbitration.isValid
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cache.io.cpu.cmd.isFiring := prefetch.arbitration.isFiring
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cache.io.cpu.cmd.address := prefetch.output(PC)
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prefetch.arbitration.haltIt setWhen(cache.io.cpu.cmd.haltIt)
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//Connect fetch cache side
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cache.io.cpu.rsp.isValid := fetch.arbitration.isValid
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cache.io.cpu.rsp.isStuck := fetch.arbitration.isStuck
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cache.io.cpu.rsp.address := fetch.output(PC)
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fetch.arbitration.haltIt setWhen(cache.io.cpu.rsp.haltIt)
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fetch.insert(INSTRUCTION) := cache.io.cpu.rsp.data
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cache.io.flush.cmd.valid := False
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// fetch.insert(IBUS_ACCESS_ERROR) := iRsp.error
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// if(catchAccessFault){
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// decodeExceptionPort.valid := decode.arbitration.isValid && decode.input(IBUS_ACCESS_ERROR)
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// decodeExceptionPort.code := 1
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// decodeExceptionPort.badAddr := decode.input(PC)
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// }
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}
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}
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case class InstructionCacheCpuCmd(p : InstructionCacheConfig) extends Bundle with IMasterSlave{
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val isValid = Bool
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val isFiring = Bool
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val haltIt = Bool
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val address = UInt(p.addressWidth bit)
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override def asMaster(): Unit = {
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out(isValid, isFiring, address)
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in(haltIt)
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}
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}
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case class InstructionCacheCpuRsp(p : InstructionCacheConfig) extends Bundle with IMasterSlave {
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val isValid = Bool
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val haltIt = Bool
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val isStuck = Bool
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val address = UInt(p.addressWidth bit)
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val data = Bits(32 bit)
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override def asMaster(): Unit = {
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out(isValid, isStuck, address)
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in(haltIt, data)
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}
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}
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case class InstructionCacheCpuBus(p : InstructionCacheConfig) extends Bundle with IMasterSlave{
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val cmd = InstructionCacheCpuCmd(p)
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val rsp = InstructionCacheCpuRsp(p)
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override def asMaster(): Unit = {
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master(cmd)
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master(rsp)
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}
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}
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case class InstructionCacheMemCmd(p : InstructionCacheConfig) extends Bundle{
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val address = UInt(p.addressWidth bit)
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}
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case class InstructionCacheMemRsp(p : InstructionCacheConfig) extends Bundle{
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val data = Bits(32 bit)
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}
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case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle with IMasterSlave{
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val cmd = Stream (InstructionCacheMemCmd(p))
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val rsp = Flow (InstructionCacheMemRsp(p))
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override def asMaster(): Unit = {
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master(cmd)
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slave(rsp)
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}
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}
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case class InstructionCacheFlushBus() extends Bundle with IMasterSlave{
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val cmd = Event
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val rsp = Bool
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override def asMaster(): Unit = {
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master(cmd)
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in(rsp)
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}
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}
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class InstructionCache(p : InstructionCacheConfig) extends Component{
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import p._
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assert(wayCount == 1)
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assert(cpuDataWidth == memDataWidth)
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val io = new Bundle{
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val flush = slave(InstructionCacheFlushBus())
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val cpu = slave(InstructionCacheCpuBus(p))
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val mem = master(InstructionCacheMemBus(p))
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}
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// val haltCpu = False
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val lineWidth = bytePerLine*8
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val lineCount = cacheSize/bytePerLine
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val wordWidth = Math.max(memDataWidth,32)
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val wordWidthLog2 = log2Up(wordWidth)
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val wordPerLine = lineWidth/wordWidth
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val bytePerWord = wordWidth/8
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val wayLineCount = lineCount/wayCount
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val wayLineLog2 = log2Up(wayLineCount)
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val wayWordCount = wayLineCount * wordPerLine
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val tagRange = addressWidth-1 downto log2Up(wayLineCount*bytePerLine)
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val lineRange = tagRange.low-1 downto log2Up(bytePerLine)
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val wordRange = log2Up(bytePerLine)-1 downto log2Up(bytePerWord)
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class LineInfo() extends Bundle{
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val valid = Bool
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val address = UInt(tagRange.length bit)
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}
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val ways = Array.fill(wayCount)(new Area{
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val tags = Mem(new LineInfo(),wayLineCount)
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val datas = Mem(Bits(wordWidth bit),wayWordCount)
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})
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io.cpu.cmd.haltIt := False
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val lineLoader = new Area{
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val requestIn = Stream(wrap(new Bundle{
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val addr = UInt(addressWidth bit)
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}))
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if(wrappedMemAccess)
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io.mem.cmd.address := requestIn.addr(tagRange.high downto wordRange.low) @@ U(0,wordRange.low bit)
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else
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io.mem.cmd.address := requestIn.addr(tagRange.high downto lineRange.low) @@ U(0,lineRange.low bit)
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val flushCounter = Reg(UInt(log2Up(wayLineCount) + 1 bit)) init(0)
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when(!flushCounter.msb){
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io.cpu.cmd.haltIt := True
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flushCounter := flushCounter + 1
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}
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when(!RegNext(flushCounter.msb)){
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io.cpu.cmd.haltIt := True
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}
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val flushFromInterface = RegInit(False)
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when(io.flush.cmd.valid){
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io.cpu.cmd.haltIt := True
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when(io.flush.cmd.ready){
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flushCounter := 0
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flushFromInterface := True
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}
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}
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io.flush.rsp := flushCounter.msb.rise && flushFromInterface
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val lineInfoWrite = new LineInfo()
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lineInfoWrite.valid := flushCounter.msb
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lineInfoWrite.address := requestIn.addr(tagRange)
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when(requestIn.fire || !flushCounter.msb){
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val tagsAddress = Mux(flushCounter.msb,requestIn.addr(lineRange),flushCounter(flushCounter.high-1 downto 0))
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ways(0).tags(tagsAddress) := lineInfoWrite //TODO
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}
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val request = requestIn.haltWhen(!io.mem.cmd.ready).stage()
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io.mem.cmd.valid := requestIn.valid && !request.isStall
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val wordIndex = Reg(UInt(log2Up(wordPerLine) bit))
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val loadedWordsNext = Bits(wordPerLine bit)
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val loadedWords = RegNext(loadedWordsNext)
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val loadedWordsReadable = RegNext(loadedWords)
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loadedWordsNext := loadedWords
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when(io.mem.rsp.fire){
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wordIndex := wordIndex + 1
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loadedWordsNext(wordIndex) := True
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ways(0).datas(request.addr(lineRange) @@ wordIndex) := io.mem.rsp.data //TODO
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}
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val readyDelay = Reg(UInt(1 bit))
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when(loadedWordsNext === B(loadedWordsNext.range -> true)){
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readyDelay := readyDelay + 1
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}
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request.ready := readyDelay === 1
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when(requestIn.ready){
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wordIndex := io.mem.cmd.address(wordRange)
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loadedWords := 0
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loadedWordsReadable := 0
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readyDelay := 0
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}
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}
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val task = new Area{
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val waysHitValid = False
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val waysHitWord = Bits(wordWidth bit)
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waysHitWord.assignDontCare()
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val waysRead = for(way <- ways) yield new Area{
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val readAddress = Mux(io.cpu.rsp.isStuck,io.cpu.rsp.address,io.cpu.cmd.address)
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val tag = way.tags.readSync(readAddress(lineRange))
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val data = way.datas.readSync(readAddress(lineRange.high downto wordRange.low))
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// val readAddress = request.address
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// val tag = way.tags.readAsync(readAddress(lineRange))
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// val data = way.datas.readAsync(readAddress(lineRange.high downto wordRange.low))
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// way.tags.add(new AttributeString("ramstyle","no_rw_check"))
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// way.datas.add(new AttributeString("ramstyle","no_rw_check"))
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when(tag.valid && tag.address === io.cpu.rsp.address(tagRange)) {
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waysHitValid := True
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waysHitWord := data
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}
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}
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val loaderHitValid = lineLoader.request.valid && lineLoader.request.addr(tagRange) === io.cpu.rsp.address(tagRange)
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val loaderHitReady = lineLoader.loadedWordsReadable(io.cpu.rsp.address(wordRange))
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io.cpu.rsp.haltIt := io.cpu.rsp.isValid && !( waysHitValid && !(loaderHitValid && !loaderHitReady))
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io.cpu.rsp.data := waysHitWord //TODO
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lineLoader.requestIn.valid := io.cpu.rsp.isValid && ! waysHitValid
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lineLoader.requestIn.addr := io.cpu.rsp.address
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}
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io.flush.cmd.ready := !(lineLoader.request.valid || io.cpu.rsp.isValid)
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}
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object InstructionCacheMain{
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class TopLevel extends Component{
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implicit val p = InstructionCacheConfig(
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cacheSize =4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32)
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// val io = new Bundle{
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// val cpu = slave(InstructionCacheCpuBus())
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// val mem = master(InstructionCacheMemBus())
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// }
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val cache = new InstructionCache(p)
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// cache.io.cpu.cmd <-< io.cpu.cmd
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// cache.io.mem.cmd >-> io.mem.cmd
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// cache.io.mem.rsp <-< io.mem.rsp
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// cache.io.cpu.rsp >-> io.cpu.rsp
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// when(cache.io.cpu.rsp.valid){
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// cache.io.cpu.cmd.valid := RegNext(cache.io.cpu.cmd.valid)
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// cache.io.cpu.cmd.address := RegNext(cache.io.cpu.cmd.address)
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// }
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}
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def main(args: Array[String]) {
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implicit val p = InstructionCacheConfig(
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cacheSize =4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32)
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// val io = new Bundle{
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// val cpu = slave(InstructionCacheCpuBus())
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// val mem = master(InstructionCacheMemBus())
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// }
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SpinalVhdl(new InstructionCache(p))
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}
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}
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@ -44,8 +44,8 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean)
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//Insert iRsp into INSTRUCTION
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iRsp = in(IBusSimpleRsp()).setName("iRsp")
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fetch.insert(INSTRUCTION) := iRsp.inst
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fetch.arbitration.haltIt setWhen(fetch.arbitration.isValid && !iRsp.ready)
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fetch.insert(IBUS_ACCESS_ERROR) := iRsp.error
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fetch.arbitration.haltIt setWhen(fetch.arbitration.isValid && !iRsp.ready)
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if(catchAccessFault){
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decodeExceptionPort.valid := decode.arbitration.isValid && decode.input(IBUS_ACCESS_ERROR)
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@ -30,6 +30,16 @@ object TopLevel {
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pcWidth = 32
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)
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// val iCacheConfig = InstructionCacheConfig(
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// cacheSize =4096,
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// bytePerLine =32,
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// wayCount = 1,
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// wrappedMemAccess = true,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32
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// )
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val csrConfig = MachineCsrConfig(
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mvendorid = 11,
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@ -69,9 +79,21 @@ object TopLevel {
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config.plugins ++= List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusSimplePlugin(
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interfaceKeepData = true,
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catchAccessFault = true
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// new IBusSimplePlugin(
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// interfaceKeepData = true,
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// catchAccessFault = true
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// ),
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new IBusCachedPlugin(
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catchAccessFault = false,
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cacheConfig = InstructionCacheConfig(
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cacheSize =4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32
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)
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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@ -13,9 +13,9 @@
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#include <string.h>
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#include <iostream>
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#include <fstream>
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#include <vector>
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//#define REF
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//#define TRACE
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class Memory{
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public:
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@ -133,9 +133,21 @@ double sc_time_stamp(){
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}
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class SimElement{
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public:
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virtual void onReset(){}
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virtual void preCycle(){}
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virtual void postCycle(){}
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};
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class Workspace;
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void fillSimELements(Workspace *ws);
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class Workspace{
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public:
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static uint32_t cycles;
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vector<SimElement*> simElements;
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Memory mem;
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string name;
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VVexRiscv* top;
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@ -161,6 +173,7 @@ public:
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regTraces.open (name + ".regTrace");
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memTraces.open (name + ".memTrace");
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logTraces.open (name + ".logTrace");
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fillSimELements(this);
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}
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virtual ~Workspace(){
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@ -176,8 +189,16 @@ public:
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}
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Workspace* bootAt(uint32_t pc) { bootPc = pc;}
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virtual uint32_t iRspOverride(uint32_t value) { return value; }
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virtual bool isAccessError(uint32_t addr) { return addr == 0xF00FFF60u; }
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virtual void iBusAccess(uint32_t addr, uint32_t *data, bool *error) {
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assert(addr % 4 == 0);
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*data = ( (mem[addr + 0] << 0)
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| (mem[addr + 1] << 8)
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| (mem[addr + 2] << 16)
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| (mem[addr + 3] << 24));
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*error = addr == 0xF00FFF60u;
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}
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virtual void postReset() {}
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virtual void checks(){}
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virtual void pass(){ throw success();}
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@ -203,12 +224,10 @@ public:
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// Reset
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top->clk = 0;
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top->reset = 0;
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top->iCmd_ready = 1;
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top->dCmd_ready = 1;
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top->iRsp_ready = 1;
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top->dRsp_ready = 1;
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top->iRsp_error = 0;
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top->dRsp_error = 0;
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for(SimElement* simElement : simElements) simElement->onReset();
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top->eval(); currentTime = 3;
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top->reset = 1;
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@ -232,10 +251,9 @@ public:
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try {
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// run simulation for 100 clock periods
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uint32_t iRsp_inst_next = top->iRsp_inst;
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uint32_t dRsp_inst_next = VL_RANDOM_I(32);
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bool iRsp_error_next = false, dRsp_error_next = false;
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bool iRsp_ready_pending = false, dRsp_ready_pending = false;
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bool dRsp_error_next = false;
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bool dRsp_ready_pending = false;
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for (i = 16; i < timeout*2; i+=2) {
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mTime = i/2;
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#ifdef CSR
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@ -251,26 +269,15 @@ public:
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dump(i);
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top->clk = 0;
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top->eval(); top->eval();top->eval();
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top->eval();
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dump(i + 1);
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if (top->iCmd_valid && top->iCmd_ready && !iRsp_ready_pending) {
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assertEq(top->iCmd_payload_pc & 3,0);
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iRsp_ready_pending = true;
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//printf("%d\n",top->iCmd_payload_pc);
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iRsp_inst_next = iRspOverride((mem[top->iCmd_payload_pc + 0] << 0)
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| (mem[top->iCmd_payload_pc + 1] << 8)
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| (mem[top->iCmd_payload_pc + 2] << 16)
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| (mem[top->iCmd_payload_pc + 3] << 24));
|
||||
iRsp_error_next = isAccessError(top->iCmd_payload_pc);
|
||||
}
|
||||
|
||||
if (top->dCmd_valid && top->dCmd_ready && ! dRsp_ready_pending) {
|
||||
dRsp_ready_pending = true;
|
||||
dRsp_inst_next = VL_RANDOM_I(32);
|
||||
//printf("%d\n",top->iCmd_payload_pc);
|
||||
uint32_t addr = top->dCmd_payload_address;
|
||||
dRsp_error_next = isAccessError(addr);
|
||||
if(top->dCmd_payload_wr){
|
||||
|
|
@ -334,19 +341,16 @@ public:
|
|||
" : reg[" << (uint32_t)top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address << "] = " << top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_data << endl;
|
||||
}
|
||||
|
||||
for(SimElement* simElement : simElements) simElement->preCycle();
|
||||
checks();
|
||||
top->clk = 1;
|
||||
top->eval(); top->eval();
|
||||
top->eval();
|
||||
|
||||
cycles += 1;
|
||||
top->iRsp_ready = !iRsp_ready_pending;
|
||||
|
||||
for(SimElement* simElement : simElements) simElement->postCycle();
|
||||
|
||||
top->dRsp_ready = 0;
|
||||
if(iRsp_ready_pending && (!iStall || VL_RANDOM_I(8) < 100)){
|
||||
top->iRsp_inst = iRsp_inst_next;
|
||||
iRsp_ready_pending = false;
|
||||
top->iRsp_ready = 1;
|
||||
top->iRsp_error = iRsp_error_next;
|
||||
}
|
||||
if(dRsp_ready_pending && (!dStall || VL_RANDOM_I(8) < 100)){
|
||||
top->dRsp_data = dRsp_inst_next;
|
||||
dRsp_ready_pending = false;
|
||||
|
|
@ -356,7 +360,6 @@ public:
|
|||
top->dRsp_data = VL_RANDOM_I(32);
|
||||
}
|
||||
|
||||
if(iStall) top->iCmd_ready = VL_RANDOM_I(8) < 100 && !iRsp_ready_pending;
|
||||
if(dStall) top->dCmd_ready = VL_RANDOM_I(8) < 100 && !dRsp_ready_pending;
|
||||
|
||||
|
||||
|
|
@ -382,6 +385,104 @@ public:
|
|||
return this;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
|
||||
#ifdef IBUS_SIMPLE
|
||||
class IBusSimple : public SimElement{
|
||||
public:
|
||||
uint32_t inst_next = VL_RANDOM_I(32);
|
||||
bool error_next = false;
|
||||
bool pending = false;
|
||||
|
||||
Workspace *ws;
|
||||
VVexRiscv* top;
|
||||
IBusSimple(Workspace* ws){
|
||||
this->ws = ws;
|
||||
this->top = ws->top;
|
||||
}
|
||||
|
||||
virtual void onReset(){
|
||||
top->iCmd_ready = 1;
|
||||
top->iRsp_ready = 1;
|
||||
}
|
||||
|
||||
virtual void preCycle(){
|
||||
if (top->iCmd_valid && top->iCmd_ready && !pending) {
|
||||
assertEq(top->iCmd_payload_pc & 3,0);
|
||||
pending = true;
|
||||
ws->iBusAccess(top->iCmd_payload_pc,&inst_next,&error_next);
|
||||
}
|
||||
}
|
||||
|
||||
virtual void postCycle(){
|
||||
top->iRsp_ready = !pending;
|
||||
if(pending && (!ws->iStall || VL_RANDOM_I(8) < 100)){
|
||||
top->iRsp_inst = inst_next;
|
||||
pending = false;
|
||||
top->iRsp_ready = 1;
|
||||
top->iRsp_error = error_next;
|
||||
}
|
||||
if(ws->iStall) top->iCmd_ready = VL_RANDOM_I(8) < 100 && !pending;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef IBUS_CACHED
|
||||
class IBusCached : public SimElement{
|
||||
public:
|
||||
uint32_t inst_next = VL_RANDOM_I(32);
|
||||
bool error_next = false;
|
||||
uint32_t pendingCount = 0;
|
||||
uint32_t address;
|
||||
|
||||
Workspace *ws;
|
||||
VVexRiscv* top;
|
||||
IBusCached(Workspace* ws){
|
||||
this->ws = ws;
|
||||
this->top = ws->top;
|
||||
}
|
||||
|
||||
|
||||
virtual void onReset(){
|
||||
top->iBus_cmd_ready = 1;
|
||||
top->iBus_rsp_valid = 0;
|
||||
}
|
||||
|
||||
virtual void preCycle(){
|
||||
if (top->iBus_cmd_valid && top->iBus_cmd_ready && pendingCount == 0) {
|
||||
assertEq(top->iBus_cmd_payload_address & 3,0);
|
||||
pendingCount = 8;
|
||||
address = top->iBus_cmd_payload_address;
|
||||
}
|
||||
}
|
||||
|
||||
virtual void postCycle(){
|
||||
bool dummy;
|
||||
top->iBus_rsp_valid = 0;
|
||||
if(pendingCount != 0 && (!ws->iStall || VL_RANDOM_I(8) < 100)){
|
||||
ws->iBusAccess(address,&top->iBus_rsp_payload_data,&dummy);
|
||||
pendingCount--;
|
||||
address = (address & ~0x1F) + ((address + 4) & 0x1F);
|
||||
top->iBus_rsp_valid = 1;
|
||||
}
|
||||
if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I(8) < 100 && pendingCount == 0;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
void fillSimELements(Workspace *ws){
|
||||
|
||||
#ifdef IBUS_SIMPLE
|
||||
ws->simElements.push_back(new IBusSimple(ws));
|
||||
#endif
|
||||
#ifdef IBUS_CACHED
|
||||
ws->simElements.push_back(new IBusCached(ws));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
uint32_t Workspace::cycles = 0;
|
||||
|
||||
#ifndef REF
|
||||
|
|
@ -474,12 +575,9 @@ public:
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
virtual uint32_t iRspOverride(uint32_t value) {
|
||||
switch(value){
|
||||
case 0x0ff0000f: return 0x00000013;
|
||||
default: return value;
|
||||
}
|
||||
virtual void iBusAccess(uint32_t addr, uint32_t *data, bool *error){
|
||||
Workspace::iBusAccess(addr,data,error);
|
||||
if(*data == 0x0ff0000f) *data = 0x00000013;
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
|
@ -600,6 +698,7 @@ long timer_end(struct timespec start_time){
|
|||
int main(int argc, char **argv, char **env) {
|
||||
Verilated::randReset(2);
|
||||
Verilated::commandArgs(argc, argv);
|
||||
|
||||
printf("BOOT\n");
|
||||
timespec startedAt = timer_start();
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
IBUS=IBUS_CACHED
|
||||
DBUS=DBUS_SIMPLE
|
||||
TRACE=no
|
||||
TRACE_START=0
|
||||
CSR=yes
|
||||
|
|
@ -7,6 +9,8 @@ REDO=10
|
|||
REF=no
|
||||
TRACE_WITH_TIME=no
|
||||
|
||||
ADDCFLAGS += -CFLAGS -D${IBUS}
|
||||
ADDCFLAGS += -CFLAGS -D${DBUS}
|
||||
ADDCFLAGS += -CFLAGS -DREDO=${REDO}
|
||||
ifeq ($(DHRYSTONE),yes)
|
||||
ADDCFLAGS += -CFLAGS -DDHRYSTONE
|
||||
|
|
|
|||
Loading…
Reference in New Issue