Revert CfuPlugin
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@ -1,6 +1,6 @@
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package vexriscv.plugin
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import vexriscv.{DecoderService, ExceptionCause, ExceptionService, JumpService, Stage, Stageable, VexRiscv}
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import vexriscv.{DecoderService, ExceptionCause, ExceptionService, Stage, Stageable, VexRiscv}
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.bmb.WeakConnector
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@ -92,9 +92,7 @@ object CfuPlugin{
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case class CfuPluginEncoding(instruction : MaskedLiteral,
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functionId : List[Range],
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input2Kind : CfuPlugin.Input2Kind.E,
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withCmd : Boolean = true,
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withRsp : Boolean = true){
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input2Kind : CfuPlugin.Input2Kind.E){
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val functionIdWidth = functionId.map(_.size).sum
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}
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@ -113,7 +111,6 @@ class CfuPlugin(val stageCount : Int,
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// assert(p.CFU_FUNCTION_ID_W == 3)
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var bus : CfuBus = null
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// var redoInterface : Flow[UInt] = null
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lazy val forkStage = pipeline.execute
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lazy val joinStage = pipeline.stages(Math.min(pipeline.stages.length - 1, pipeline.indexOf(forkStage) + stageCount))
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@ -123,46 +120,32 @@ class CfuPlugin(val stageCount : Int,
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val CFU_IN_FLIGHT = new Stageable(Bool()).setCompositeName(this, "CFU_IN_FLIGHT")
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val CFU_ENCODING = new Stageable(UInt(log2Up(encodings.size) bits)).setCompositeName(this, "CFU_ENCODING")
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val CFU_INPUT_2_KIND = new Stageable(CfuPlugin.Input2Kind()).setCompositeName(this, "CFU_INPUT_2_KIND")
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val CFU_WITH_CMD = new Stageable(Bool()).setCompositeName(this, "CFU_WITH_CMD")
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val CFU_WITH_RSP = new Stageable(Bool()).setCompositeName(this, "CFU_WITH_RSP")
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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// val pcManagerService = pipeline.service(classOf[JumpService])
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// if(encodings.contains(_.cmd)redoInterface = pcManagerService.createJumpInterface(pipeline.writeBack)
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bus = master(CfuBus(p))
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val decoderService = pipeline.service(classOf[DecoderService])
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decoderService.addDefault(CFU_ENABLE, False)
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decoderService.addDefault(CFU_WITH_CMD, False)
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decoderService.addDefault(CFU_WITH_RSP, False)
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for((encoding, id) <- encodings.zipWithIndex){
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var actions : List[(Stageable[_ <: BaseType], Any)] = List(
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var actions = List(
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CFU_ENABLE -> True,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> Bool(stageCount == 0),
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BYPASSABLE_MEMORY_STAGE -> Bool(stageCount <= 1),
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RS1_USE -> True,
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CFU_ENCODING -> U(id),
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CFU_WITH_CMD -> Bool(encoding.withCmd),
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CFU_WITH_RSP -> Bool(encoding.withRsp)
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CFU_INPUT_2_KIND -> encoding.input2Kind()
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)
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if(encoding.withCmd){
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actions :+= RS1_USE -> True
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actions :+= CFU_INPUT_2_KIND -> encoding.input2Kind()
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encoding.input2Kind match {
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case CfuPlugin.Input2Kind.RS =>
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actions :+= RS2_USE -> True
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case CfuPlugin.Input2Kind.IMM_I =>
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}
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}
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if(encoding.withRsp){
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actions :+= REGFILE_WRITE_VALID -> True
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actions :+= BYPASSABLE_EXECUTE_STAGE -> Bool(stageCount == 0)
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actions :+= BYPASSABLE_MEMORY_STAGE -> Bool(stageCount <= 1)
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}
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decoderService.add(
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key = encoding.instruction,
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@ -208,7 +191,7 @@ class CfuPlugin(val stageCount : Int,
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import forkStage._
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input(CFU_ENABLE).clearWhen(!input(LEGAL_INSTRUCTION))
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val hazard = stages.dropWhile(_ != forkStage).tail.map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR
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val scheduleWish = arbitration.isValid && input(CFU_ENABLE) && input(CFU_WITH_CMD)
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val scheduleWish = arbitration.isValid && input(CFU_ENABLE)
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val schedule = scheduleWish && !hazard
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arbitration.haltItself setWhen(scheduleWish && hazard)
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@ -251,13 +234,12 @@ class CfuPlugin(val stageCount : Int,
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bus.rsp.combStage()
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}
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val hazard = stages.dropWhile(_ != joinStage).tail.map(s => s.arbitration.isValid && s.input(HAS_SIDE_EFFECT)).orR
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rsp.ready := False
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when((arbitration.isValid || input(CFU_IN_FLIGHT)) && input(CFU_WITH_RSP)){
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arbitration.haltItself setWhen(!rsp.valid || hazard)
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rsp.ready := !arbitration.isStuckByOthers && !hazard
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when(input(CFU_IN_FLIGHT)){
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arbitration.haltItself setWhen(!rsp.valid)
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rsp.ready := !arbitration.isStuckByOthers
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output(REGFILE_WRITE_DATA) := rsp.outputs(0)
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if(p.CFU_WITH_STATUS) when(rsp.fire){
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if(p.CFU_WITH_STATUS) when(arbitration.isFiring){
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switch(rsp.status) {
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for (i <- 1 to 6) is(i) {
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csr.status.flags(i-1) := True
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