Add missing parameter jtagHeaderIgnoreWidth

doc/nativeJtag/README.md

@@ -49,7 +49,7 @@ as given could move with future changes to the file:
 ```
 [254]	val jtagCtrl = JtagTapInstructionCtrl()
 [255]	val tap = jtagCtrl.fromXilinxBscane2(userId = 2)
-[256]	jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK))
+[256]	jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK),0)
 ```
 Changing the above lines, removes the Murax SoC’s JTAG ports as pins of the FPGA and inserts the BSCANE2 Xilinx
 Debug IP to which the JTAG signals are now connected.

src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala

@@ -168,7 +168,7 @@ object VexRiscvAhbLite3{
 //            // On Artix FPGA jtag :
 //            val jtagCtrl = JtagTapInstructionCtrl()
 //            val tap = jtagCtrl.fromXilinxBscane2(userId = 1)
-//            jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK))
+//            jtagCtrl <> plugin.io.bus.fromJtagInstructionCtrl(ClockDomain(tap.TCK),0)
           }
           case _ =>
         }