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Bring freertos back in tests 

Better travis test range
This commit is contained in:
Charles Papon 2019-04-21 12:50:28 +02:00
parent edde3e3011
commit 963805ad48
5 changed files with 123 additions and 81 deletions
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14
.travis.yml
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@ -35,32 +35,32 @@ jobs:
- make verilator_binary
- &test
stage: Test
name: TEST_DHRYSTONE
name: Dhrystone
script:
- make regression_dhrystone -C scripts/regression
- <<: *test
stage: Test
name: TEST_BAREMETAL
name: Baremetal
script:
- make regression_random_baremetal -C scripts/regression
- <<: *test
stage: Test
name: TEST_BAREMETAL
name: Machine OS
script:
- make regression_random_baremetal -C scripts/regression
- make regression_random_machine_os -C scripts/regression
- <<: *test
stage: Test
name: TEST_MIXED
name: Mixed
script:
- make regression_random -C scripts/regression
- <<: *test
stage: Test
name: TEST_LINUX
name: Linux
script:
- make regression_random_linux -C scripts/regression
- <<: *test
stage: Test
name: TEST_LINUX
name: Linux
script:
- make regression_random_linux -C scripts/regression

25
scripts/regression/regression.mk
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@ -4,29 +4,42 @@
regression_random:
cd ../..
export VEXRISCV_REGRESSION_CONFIG_COUNT=4
export VEXRISCV_REGRESSION_FREERTOS_COUNT=no
export VEXRISCV_REGRESSION_FREERTOS_COUNT=1
export VEXRISCV_REGRESSION_ZEPHYR_COUNT=4
export VEXRISCV_REGRESSION_THREAD_COUNT=1
sbt "testOnly vexriscv.TestIndividualFeatures"
regression_random_linux:
cd ../..
export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=1.0
export VEXRISCV_REGRESSION_CONFIG_COUNT=3
export VEXRISCV_REGRESSION_FREERTOS_COUNT=no
export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=1.0
export VEXRISCV_REGRESSION_FREERTOS_COUNT=2
export VEXRISCV_REGRESSION_ZEPHYR_COUNT=4
export VEXRISCV_REGRESSION_THREAD_COUNT=1
sbt "testOnly vexriscv.TestIndividualFeatures"
regression_random_machine_os:
cd ../..
export VEXRISCV_REGRESSION_CONFIG_COUNT=30
export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=0.0
export VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE = 1.0
export VEXRISCV_REGRESSION_FREERTOS_COUNT=2
export VEXRISCV_REGRESSION_ZEPHYR_COUNT=4
export VEXRISCV_REGRESSION_THREAD_COUNT=1
sbt "testOnly vexriscv.TestIndividualFeatures"
regression_random_baremetal:
cd ../..
export VEXRISCV_REGRESSION_CONFIG_COUNT=40
export VEXRISCV_REGRESSION_CONFIG_LINUX_RATE=0.0
export VEXRISCV_REGRESSION_CONFIG_COUNT=50
export VEXRISCV_REGRESSION_FREERTOS_COUNT=no
export VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE = 0.0
export VEXRISCV_REGRESSION_FREERTOS_COUNT=1
export VEXRISCV_REGRESSION_ZEPHYR_COUNT=no
export VEXRISCV_REGRESSION_THREAD_COUNT=1
sbt "testOnly vexriscv.TestIndividualFeatures"
regression_dhrystone:
cd ../..
sbt "testOnly vexriscv.DhrystoneBench"

15
src/test/cpp/regression/main.cpp
View File

@ -229,6 +229,13 @@ class success : public std::exception { };
#define SSTATUS_SPIE 0x00000020
#define SSTATUS_SPP 0x00000100
#ifdef SUPERVISOR
#define MSTATUS_READ_MASK 0xFFFFFFFF
#else
#define MSTATUS_READ_MASK 0x1888
#endif
class RiscvGolden {
public:
int32_t pc, lastPc;
@ -528,7 +535,7 @@ public:
virtual bool csrRead(int32_t csr, uint32_t *value){
if(((csr >> 8) & 0x3) > privilege) return true;
switch(csr){
case MSTATUS: *value = status.raw; break;
case MSTATUS: *value = status.raw & MSTATUS_READ_MASK; break;
case MIP: *value = getIp().raw; break;
case MIE: *value = ie.raw; break;
case MTVEC: *value = mtvec.raw; break;
@ -3502,7 +3509,7 @@ static void multiThreading(queue<std::function<void()>> *lambdas, std::mutex *mu
uint32_t seed = SEED + counter;
counter++;
srand48(seed);
printf("FREERTOS_SEED=%d \n", seed);
printf("MT_SEED=%d \n", seed);
#endif
std::function<void()> lambda = lambdas->front();
lambdas->pop();
@ -3667,7 +3674,7 @@ int main(int argc, char **argv, char **env) {
redo(REDO, Compliance(name).run();)
}
#endif
#ifdef CSR
#if defined(CSR) && !defined(CSR_SKIP_TEST)
for(const string &name : complianceTestCsr){
redo(REDO, Compliance(name).run();)
}
@ -3702,7 +3709,7 @@ int main(int argc, char **argv, char **env) {
redo(REDO,RiscvTest("rv32uc-p-rvc").bootAt(0x800000FCu)->run());
#endif
#ifdef CSR
#if defined(CSR) && !defined(CSR_SKIP_TEST)
#ifndef COMPRESSED
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
8,6,9,6,10,4,11,4, 12,13,0, 14,2, 15,5,16,17,1 };

5
src/test/cpp/regression/makefile
View File

@ -10,6 +10,7 @@ ISA_TEST?=yes
MUL?=yes
DIV?=yes
CSR?=yes
CSR_SKIP_TEST?=no
EBREAK?=no
FENCEI?=no
MMU?=yes
@ -173,6 +174,10 @@ ifeq ($(CSR),yes)
ADDCFLAGS += -CFLAGS -DCSR
endif
ifeq ($(CSR_SKIP_TEST),yes)
ADDCFLAGS += -CFLAGS -DCSR_SKIP_TEST
endif
ifeq ($(LRSC),yes)
ADDCFLAGS += -CFLAGS -DLRSC

145
src/test/scala/vexriscv/TestIndividualFeatures.scala
View File

@ -45,8 +45,8 @@ class VexRiscvUniverse extends ConfigUniverse
object VexRiscvUniverse{
val CATCH_ALL = new VexRiscvUniverse
val MMU = new VexRiscvUniverse
val universes = List(CATCH_ALL, MMU)
val FORCE_MULDIV = new VexRiscvUniverse
val SUPERVISOR = new VexRiscvUniverse
}
@ -86,57 +86,62 @@ class BranchDimension extends VexRiscvDimension("Branch") {
class MulDivDimension extends VexRiscvDimension("MulDiv") {
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = random(r, List(
new VexRiscvPosition("NoMulDiv") {
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
var l = List(
new VexRiscvPosition("MulDivFpga") {
override def testParam = "MUL=yes DIV=yes"
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new MulPlugin
config.plugins += new MulDivIterativePlugin(
genMul = false,
genDiv = true,
mulUnrollFactor = 32,
divUnrollFactor = 1
)
}
},
new VexRiscvPosition("MulDivAsic") {
override def testParam = "MUL=yes DIV=yes"
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new MulDivIterativePlugin(
genMul = true,
genDiv = true,
mulUnrollFactor = 32,
divUnrollFactor = 4
)
}
},
new VexRiscvPosition("MulDivFpgaNoDsp") {
override def testParam = "MUL=yes DIV=yes"
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new MulDivIterativePlugin(
genMul = true,
genDiv = true,
mulUnrollFactor = 1,
divUnrollFactor = 1
)
}
},
new VexRiscvPosition("MulDivFpgaNoDspFastMul") {
override def testParam = "MUL=yes DIV=yes"
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new MulDivIterativePlugin(
genMul = true,
genDiv = true,
mulUnrollFactor = 8,
divUnrollFactor = 1
)
}
}
)
if(!universes.contains(VexRiscvUniverse.FORCE_MULDIV)) l = new VexRiscvPosition("NoMulDiv") {
override def applyOn(config: VexRiscvConfig): Unit = {}
override def testParam = "MUL=no DIV=no"
},
new VexRiscvPosition("MulDivFpga") {
override def testParam = "MUL=yes DIV=yes"
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new MulPlugin
config.plugins += new MulDivIterativePlugin(
genMul = false,
genDiv = true,
mulUnrollFactor = 32,
divUnrollFactor = 1
)
}
},
new VexRiscvPosition("MulDivAsic") {
override def testParam = "MUL=yes DIV=yes"
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new MulDivIterativePlugin(
genMul = true,
genDiv = true,
mulUnrollFactor = 32,
divUnrollFactor = 4
)
}
},
new VexRiscvPosition("MulDivFpgaNoDsp") {
override def testParam = "MUL=yes DIV=yes"
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new MulDivIterativePlugin(
genMul = true,
genDiv = true,
mulUnrollFactor = 1,
divUnrollFactor = 1
)
}
},
new VexRiscvPosition("MulDivFpgaNoDspFastMul") {
override def testParam = "MUL=yes DIV=yes"
override def applyOn(config: VexRiscvConfig): Unit = {
config.plugins += new MulDivIterativePlugin(
genMul = true,
genDiv = true,
mulUnrollFactor = 8,
divUnrollFactor = 1
)
}
}
))
} :: l
random(r, l)
}
}
trait InstructionAnticipatedPosition{
@ -266,7 +271,7 @@ class IBusDimension extends VexRiscvDimension("IBus") {
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
val mmuConfig = if(catchAll) MmuPortConfig( portTlbSize = 4) else null
val mmuConfig = if(universes.contains(VexRiscvUniverse.MMU)) MmuPortConfig( portTlbSize = 4) else null
if(r.nextDouble() < 0.5){
val latency = r.nextInt(5) + 1
@ -347,7 +352,7 @@ class DBusDimension extends VexRiscvDimension("DBus") {
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
val mmuConfig = if(catchAll) MmuPortConfig( portTlbSize = 4) else null
val mmuConfig = if(universes.contains(VexRiscvUniverse.MMU)) MmuPortConfig( portTlbSize = 4) else null
if(r.nextDouble() < 0.4){
val withLrSc = catchAll
@ -403,9 +408,7 @@ class DBusDimension extends VexRiscvDimension("DBus") {
class MmuDimension extends VexRiscvDimension("DBus") {
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
if(catchAll) {
if(universes.contains(VexRiscvUniverse.MMU)) {
new VexRiscvPosition("WithMmu") {
override def testParam = "MMU=yes"
@ -437,15 +440,21 @@ trait CatchAllPosition
class CsrDimension(freertos : String, zephyr : String) extends VexRiscvDimension("Csr") {
override def randomPositionImpl(universes: Seq[ConfigUniverse], r: Random) = {
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
if(catchAll){
new VexRiscvPosition("All") with CatchAllPosition{
val supervisor = universes.contains(VexRiscvUniverse.SUPERVISOR)
if(supervisor){
new VexRiscvPosition("Supervisor") with CatchAllPosition{
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.linuxFull(0x80000020l))
override def testParam = s"FREERTOS=$freertos ZEPHYR=$zephyr LINUX_REGRESSION=yes SUPERVISOR=yes"
}
} else if(r.nextDouble() < 0.2){
} else if(catchAll){
new VexRiscvPosition("MachineOs") with CatchAllPosition{
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.all(0x80000020l))
override def testParam = s"CSR=yes FREERTOS=$freertos ZEPHYR=$zephyr"
}
} else if(r.nextDouble() < 0.3){
new VexRiscvPosition("AllNoException") with CatchAllPosition{
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new CsrPlugin(CsrPluginConfig.all(0x80000020l).noException)
override def testParam = "CSR=no FREERTOS=no"
override def testParam = s"CSR=yes CSR_SKIP_TEST=yes FREERTOS=$freertos"
}
} else {
new VexRiscvPosition("None") {
@ -516,7 +525,7 @@ class TestIndividualFeatures extends FunSuite {
new HazardDimension,
new RegFileDimension,
new SrcDimension,
new CsrDimension("no", sys.env.getOrElse("VEXRISCV_REGRESSION_ZEPHYR_COUNT", "4")),//sys.env.getOrElse("VEXRISCV_REGRESSION_FREERTOS_COUNT", "4")), TODO
new CsrDimension(sys.env.getOrElse("VEXRISCV_REGRESSION_FREERTOS_COUNT", "1"), sys.env.getOrElse("VEXRISCV_REGRESSION_ZEPHYR_COUNT", "4")),
new DecoderDimension,
new DebugDimension,
new MmuDimension
@ -572,9 +581,9 @@ class TestIndividualFeatures extends FunSuite {
val seed = Random.nextLong()
// val testId = Some(mutable.HashSet(18,34,77,85,118,129,132,134,152,167,175,188,191,198,199)) //37/29 sp_flop_rv32i_O3
//val testId = Some(mutable.HashSet(18))
//val testId = Some(mutable.HashSet(3))
// val testId = Some(mutable.HashSet(129, 134))
// val seed = -2412372746600605141l
// val seed = -1580866821569084523l
val rand = new Random(seed)
@ -586,7 +595,15 @@ class TestIndividualFeatures extends FunSuite {
for(i <- 0 until sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_COUNT", "100").toInt){
var positions : List[VexRiscvPosition] = null
var universe = mutable.HashSet[VexRiscvUniverse]()
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_LINUX_RATE", "0.5").toDouble > Math.random()) universe += VexRiscvUniverse.CATCH_ALL
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_LINUX_RATE", "0.3").toDouble > Math.random()) {
universe += VexRiscvUniverse.CATCH_ALL
universe += VexRiscvUniverse.MMU
universe += VexRiscvUniverse.FORCE_MULDIV
universe += VexRiscvUniverse.SUPERVISOR
}
if(sys.env.getOrElse("VEXRISCV_REGRESSION_CONFIG_MACHINE_OS_RATE", "0.5").toDouble > Math.random()) {
universe += VexRiscvUniverse.CATCH_ALL
}
do{
positions = dimensions.map(d => d.randomPosition(universe.toList, rand))