Murax on Digilent Arty A7-35
This commit is contained in:
sebastien-riou
parent
195318b665
commit
97b2838d18
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This example is for the Digilent ARTY A7 35T board.
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# Using the example
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## Before Starting
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You should make sure you have the following tools installed:
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* vivado 2018.1 or later
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* riscv toolchain (riscv64-unknown-elf)
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* sbt
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## Board setup
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Make sure you have a rev E board. If you have a later version check that the
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flash part is S25FL128SAGMF100.
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Jumper settings for board rev E:
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* Disconnect anything from the connectors (Pmod, Arduino)
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* Jumpers: JP1 and JP2 on, others off.
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## Building
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You should be able to just type `make` and get output similar to this;
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```
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...
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Memory region Used Size Region Size %age Used
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RAM: 896 B 2 KB 43.75%
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...
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---------------------------------------------------------------------------------
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Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1457.785 ; gain = 243.430 ; free physical = 17940 ; free virtual = 57159
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---------------------------------------------------------------------------------
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...
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---------------------------------------------------------------------------------
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Finished Technology Mapping : Time (s): cpu = 00:02:42 ; elapsed = 00:02:58 . Memory (MB): peak = 1986.879 ; gain = 772.523 ; free physical = 17454 ; free virtual = 56670
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---------------------------------------------------------------------------------
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...
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---------------------------------------------------------------------------------
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Finished Writing Synthesis Report : Time (s): cpu = 00:02:45 ; elapsed = 00:03:01 . Memory (MB): peak = 1986.879 ; gain = 772.523 ; free physical = 17457 ; free virtual = 56673
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---------------------------------------------------------------------------------
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...
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Writing bitstream ./toplevel.bit...
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...
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mmi files generated
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...
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********************************************
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./soc_latest_sw.bit correctly generated
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********************************************
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...
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********************************************
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./soc_latest_sw.mcs correctly generated
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********************************************
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INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 04:00:50 2019...
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```
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The process should take around 8 minutes on a reasonably fast computer.
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## Programming
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### Direct FPGA RAM programming
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Run `make prog` to program the bit file directly to FPGA RAM.
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You should get output like the following;
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```
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...
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****** Xilinx hw_server v2018.1
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**** Build date : Apr 4 2018-18:56:09
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210319AB569AA
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INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
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WARNING: [Labtools 27-3361] The debug hub core was not detected.
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Resolution:
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1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
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2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
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For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
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INFO: [Labtools 27-3164] End of startup status: HIGH
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INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 04:01:36 2019...
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```
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After programming the LED4~LED7 shall show some activity.
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### QSPI flash programming
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Run `make flash` to program the bit file to the QSPI flash.
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You should get output like the following;
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```
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...
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****** Xilinx hw_server v2018.1
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**** Build date : Apr 4 2018-18:56:09
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210319AB569AA
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INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
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...
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INFO: [Labtools 27-3164] End of startup status: HIGH
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Mfg ID : 1 Memory Type : 20 Memory Capacity : 18 Device ID 1 : 0 Device ID 2 : 0
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Performing Erase Operation...
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Erase Operation successful.
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Performing Program and Verify Operations...
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Program/Verify Operation successful.
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INFO: [Labtoolstcl 44-377] Flash programming completed successfully
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program_hw_cfgmem: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:52 . Memory (MB): peak = 1792.711 ; gain = 8.000 ; free physical = 17712 ; free virtual = 56943
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INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210319AB569AA
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...
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INFO: [Common 17-206] Exiting Vivado at Thu Nov 28 04:06:28 2019...
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```
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After programming the flash you need to press the "PROG" button on the board. Then after a second or so the "DONE" LED shall be ON and LED4~LED7 shall show some activity.
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## Connect
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After programming you should be able to connect to the serial port and have some output.
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On Linux you can do this using a command like `screen /dev/ttyUSB1`. Other good alternatives:
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* moserial (GUI)
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* picocom (can be launched via the file "picocom_arty")
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Parameters:
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* port is : /dev/ttyUSB1
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* flowcontrol : none
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* baudrate is : 115200
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* parity is : none
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* databits are : 8
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* stopbits are : 1
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@ -0,0 +1,366 @@
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set_property PACKAGE_PIN F4 [get_ports tck]
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set_property IOSTANDARD LVCMOS33 [get_ports tck]
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set_property PACKAGE_PIN D2 [get_ports tms]
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set_property IOSTANDARD LVCMOS33 [get_ports tms]
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set_property PACKAGE_PIN D4 [get_ports tdo]
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set_property IOSTANDARD LVCMOS33 [get_ports tdo]
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set_property PULLUP true [get_ports tdo]
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set_property PACKAGE_PIN E2 [get_ports tdi]
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set_property IOSTANDARD LVCMOS33 [get_ports tdi]
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set_property PACKAGE_PIN D3 [get_ports trst]
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set_property IOSTANDARD LVCMOS33 [get_ports trst]
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set_property PULLUP true [get_ports trst]
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## serial:0.tx
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set_property PACKAGE_PIN D10 [get_ports serial_tx]
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set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
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## serial:0.rx
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set_property PACKAGE_PIN A9 [get_ports serial_rx]
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set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
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## clk100:0
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set_property PACKAGE_PIN E3 [get_ports clk100]
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set_property IOSTANDARD LVCMOS33 [get_ports clk100]
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## cpu_reset:0
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set_property PACKAGE_PIN C2 [get_ports cpu_reset]
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set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
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## eth_ref_clk:0
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#set_property LOC G18 [get_ports eth_ref_clk]
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#set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk]
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## user_led:0
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set_property PACKAGE_PIN H5 [get_ports user_led0]
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set_property IOSTANDARD LVCMOS33 [get_ports user_led0]
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## user_led:1
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set_property PACKAGE_PIN J5 [get_ports user_led1]
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set_property IOSTANDARD LVCMOS33 [get_ports user_led1]
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## user_led:2
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set_property PACKAGE_PIN T9 [get_ports user_led2]
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set_property IOSTANDARD LVCMOS33 [get_ports user_led2]
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## user_led:3
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set_property PACKAGE_PIN T10 [get_ports user_led3]
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set_property IOSTANDARD LVCMOS33 [get_ports user_led3]
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## user_sw:0
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set_property PACKAGE_PIN A8 [get_ports user_sw0]
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set_property IOSTANDARD LVCMOS33 [get_ports user_sw0]
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## user_sw:1
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set_property PACKAGE_PIN C11 [get_ports user_sw1]
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set_property IOSTANDARD LVCMOS33 [get_ports user_sw1]
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## user_sw:2
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set_property PACKAGE_PIN C10 [get_ports user_sw2]
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set_property IOSTANDARD LVCMOS33 [get_ports user_sw2]
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## user_sw:3
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set_property PACKAGE_PIN A10 [get_ports user_sw3]
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set_property IOSTANDARD LVCMOS33 [get_ports user_sw3]
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## user_btn:0
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set_property PACKAGE_PIN D9 [get_ports user_btn0]
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set_property IOSTANDARD LVCMOS33 [get_ports user_btn0]
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## user_btn:1
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set_property PACKAGE_PIN C9 [get_ports user_btn1]
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set_property IOSTANDARD LVCMOS33 [get_ports user_btn1]
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## user_btn:2
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set_property PACKAGE_PIN B9 [get_ports user_btn2]
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set_property IOSTANDARD LVCMOS33 [get_ports user_btn2]
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## user_btn:3
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set_property PACKAGE_PIN B8 [get_ports user_btn3]
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set_property IOSTANDARD LVCMOS33 [get_ports user_btn3]
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## spiflash_1x:0.cs_n
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#set_property LOC L13 [get_ports spiflash_1x_cs_n]
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#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_cs_n]
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# ## spiflash_1x:0.mosi
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#set_property LOC K17 [get_ports spiflash_1x_mosi]
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#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_mosi]
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# ## spiflash_1x:0.miso
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#set_property LOC K18 [get_ports spiflash_1x_miso]
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#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_miso]
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# ## spiflash_1x:0.wp
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#set_property LOC L14 [get_ports spiflash_1x_wp]
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#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_wp]
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# ## spiflash_1x:0.hold
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#set_property LOC M14 [get_ports spiflash_1x_hold]
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#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_hold]
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# ## ddram:0.a
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#set_property LOC R2 [get_ports ddram_a[0]]
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#set_property SLEW FAST [get_ports ddram_a[0]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[0]]
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# ## ddram:0.a
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#set_property LOC M6 [get_ports ddram_a[1]]
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#set_property SLEW FAST [get_ports ddram_a[1]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[1]]
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# ## ddram:0.a
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#set_property LOC N4 [get_ports ddram_a[2]]
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#set_property SLEW FAST [get_ports ddram_a[2]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[2]]
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# ## ddram:0.a
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#set_property LOC T1 [get_ports ddram_a[3]]
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#set_property SLEW FAST [get_ports ddram_a[3]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[3]]
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# ## ddram:0.a
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#set_property LOC N6 [get_ports ddram_a[4]]
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#set_property SLEW FAST [get_ports ddram_a[4]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[4]]
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# ## ddram:0.a
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#set_property LOC R7 [get_ports ddram_a[5]]
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#set_property SLEW FAST [get_ports ddram_a[5]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[5]]
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# ## ddram:0.a
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#set_property LOC V6 [get_ports ddram_a[6]]
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#set_property SLEW FAST [get_ports ddram_a[6]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[6]]
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# ## ddram:0.a
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#set_property LOC U7 [get_ports ddram_a[7]]
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#set_property SLEW FAST [get_ports ddram_a[7]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[7]]
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# ## ddram:0.a
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#set_property LOC R8 [get_ports ddram_a[8]]
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#set_property SLEW FAST [get_ports ddram_a[8]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[8]]
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# ## ddram:0.a
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#set_property LOC V7 [get_ports ddram_a[9]]
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#set_property SLEW FAST [get_ports ddram_a[9]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[9]]
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# ## ddram:0.a
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#set_property LOC R6 [get_ports ddram_a[10]]
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#set_property SLEW FAST [get_ports ddram_a[10]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[10]]
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# ## ddram:0.a
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#set_property LOC U6 [get_ports ddram_a[11]]
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#set_property SLEW FAST [get_ports ddram_a[11]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[11]]
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# ## ddram:0.a
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#set_property LOC T6 [get_ports ddram_a[12]]
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#set_property SLEW FAST [get_ports ddram_a[12]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[12]]
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# ## ddram:0.a
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#set_property LOC T8 [get_ports ddram_a[13]]
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#set_property SLEW FAST [get_ports ddram_a[13]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_a[13]]
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# ## ddram:0.ba
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#set_property LOC R1 [get_ports ddram_ba[0]]
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#set_property SLEW FAST [get_ports ddram_ba[0]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[0]]
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# ## ddram:0.ba
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#set_property LOC P4 [get_ports ddram_ba[1]]
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#set_property SLEW FAST [get_ports ddram_ba[1]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[1]]
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# ## ddram:0.ba
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#set_property LOC P2 [get_ports ddram_ba[2]]
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#set_property SLEW FAST [get_ports ddram_ba[2]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[2]]
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# ## ddram:0.ras_n
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#set_property LOC P3 [get_ports ddram_ras_n]
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#set_property SLEW FAST [get_ports ddram_ras_n]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_ras_n]
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# ## ddram:0.cas_n
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#set_property LOC M4 [get_ports ddram_cas_n]
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#set_property SLEW FAST [get_ports ddram_cas_n]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_cas_n]
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# ## ddram:0.we_n
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#set_property LOC P5 [get_ports ddram_we_n]
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#set_property SLEW FAST [get_ports ddram_we_n]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_we_n]
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# ## ddram:0.cs_n
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#set_property LOC U8 [get_ports ddram_cs_n]
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#set_property SLEW FAST [get_ports ddram_cs_n]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_cs_n]
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# ## ddram:0.dm
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#set_property LOC L1 [get_ports ddram_dm[0]]
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#set_property SLEW FAST [get_ports ddram_dm[0]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_dm[0]]
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# ## ddram:0.dm
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#set_property LOC U1 [get_ports ddram_dm[1]]
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#set_property SLEW FAST [get_ports ddram_dm[1]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_dm[1]]
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# ## ddram:0.dq
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#set_property LOC K5 [get_ports ddram_dq[0]]
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#set_property SLEW FAST [get_ports ddram_dq[0]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[0]]
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#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
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# ## ddram:0.dq
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#set_property LOC L3 [get_ports ddram_dq[1]]
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#set_property SLEW FAST [get_ports ddram_dq[1]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[1]]
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#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
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# ## ddram:0.dq
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#set_property LOC K3 [get_ports ddram_dq[2]]
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#set_property SLEW FAST [get_ports ddram_dq[2]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[2]]
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#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
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# ## ddram:0.dq
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#set_property LOC L6 [get_ports ddram_dq[3]]
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#set_property SLEW FAST [get_ports ddram_dq[3]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[3]]
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#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
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# ## ddram:0.dq
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#set_property LOC M3 [get_ports ddram_dq[4]]
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#set_property SLEW FAST [get_ports ddram_dq[4]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[4]]
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#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
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# ## ddram:0.dq
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#set_property LOC M1 [get_ports ddram_dq[5]]
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#set_property SLEW FAST [get_ports ddram_dq[5]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[5]]
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#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
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# ## ddram:0.dq
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#set_property LOC L4 [get_ports ddram_dq[6]]
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#set_property SLEW FAST [get_ports ddram_dq[6]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[6]]
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#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
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# ## ddram:0.dq
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#set_property LOC M2 [get_ports ddram_dq[7]]
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#set_property SLEW FAST [get_ports ddram_dq[7]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[7]]
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#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
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# ## ddram:0.dq
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#set_property LOC V4 [get_ports ddram_dq[8]]
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#set_property SLEW FAST [get_ports ddram_dq[8]]
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#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[8]]
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#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
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||||
# ## ddram:0.dq
|
||||
#set_property LOC T5 [get_ports ddram_dq[9]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[9]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[9]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC U4 [get_ports ddram_dq[10]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[10]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[10]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC V5 [get_ports ddram_dq[11]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[11]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[11]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC V1 [get_ports ddram_dq[12]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[12]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[12]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC T3 [get_ports ddram_dq[13]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[13]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[13]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC U3 [get_ports ddram_dq[14]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[14]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[14]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC R3 [get_ports ddram_dq[15]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[15]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[15]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
|
||||
# ## ddram:0.dqs_p
|
||||
#set_property LOC N2 [get_ports ddram_dqs_p[0]]
|
||||
#set_property SLEW FAST [get_ports ddram_dqs_p[0]]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[0]]
|
||||
# ## ddram:0.dqs_p
|
||||
#set_property LOC U2 [get_ports ddram_dqs_p[1]]
|
||||
#set_property SLEW FAST [get_ports ddram_dqs_p[1]]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[1]]
|
||||
# ## ddram:0.dqs_n
|
||||
#set_property LOC N1 [get_ports ddram_dqs_n[0]]
|
||||
#set_property SLEW FAST [get_ports ddram_dqs_n[0]]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[0]]
|
||||
# ## ddram:0.dqs_n
|
||||
#set_property LOC V2 [get_ports ddram_dqs_n[1]]
|
||||
#set_property SLEW FAST [get_ports ddram_dqs_n[1]]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[1]]
|
||||
# ## ddram:0.clk_p
|
||||
#set_property LOC U9 [get_ports ddram_clk_p]
|
||||
#set_property SLEW FAST [get_ports ddram_clk_p]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_p]
|
||||
# ## ddram:0.clk_n
|
||||
#set_property LOC V9 [get_ports ddram_clk_n]
|
||||
#set_property SLEW FAST [get_ports ddram_clk_n]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_n]
|
||||
# ## ddram:0.cke
|
||||
#set_property LOC N5 [get_ports ddram_cke]
|
||||
#set_property SLEW FAST [get_ports ddram_cke]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_cke]
|
||||
# ## ddram:0.odt
|
||||
#set_property LOC R5 [get_ports ddram_odt]
|
||||
#set_property SLEW FAST [get_ports ddram_odt]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_odt]
|
||||
# ## ddram:0.reset_n
|
||||
#set_property LOC K6 [get_ports ddram_reset_n]
|
||||
#set_property SLEW FAST [get_ports ddram_reset_n]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_reset_n]
|
||||
# ## eth_clocks:0.tx
|
||||
#set_property LOC H16 [get_ports eth_clocks_tx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_tx]
|
||||
# ## eth_clocks:0.rx
|
||||
#set_property LOC F15 [get_ports eth_clocks_rx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_rx]
|
||||
# ## eth:0.rst_n
|
||||
#set_property LOC C16 [get_ports eth_rst_n]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rst_n]
|
||||
# ## eth:0.mdio
|
||||
#set_property LOC K13 [get_ports eth_mdio]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_mdio]
|
||||
# ## eth:0.mdc
|
||||
#set_property LOC F16 [get_ports eth_mdc]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_mdc]
|
||||
# ## eth:0.rx_dv
|
||||
#set_property LOC G16 [get_ports eth_rx_dv]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_dv]
|
||||
# ## eth:0.rx_er
|
||||
#set_property LOC C17 [get_ports eth_rx_er]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_er]
|
||||
# ## eth:0.rx_data
|
||||
#set_property LOC D18 [get_ports eth_rx_data[0]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[0]]
|
||||
# ## eth:0.rx_data
|
||||
#set_property LOC E17 [get_ports eth_rx_data[1]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[1]]
|
||||
# ## eth:0.rx_data
|
||||
#set_property LOC E18 [get_ports eth_rx_data[2]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[2]]
|
||||
# ## eth:0.rx_data
|
||||
#set_property LOC G17 [get_ports eth_rx_data[3]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[3]]
|
||||
# ## eth:0.tx_en
|
||||
#set_property LOC H15 [get_ports eth_tx_en]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_en]
|
||||
# ## eth:0.tx_data
|
||||
#set_property LOC H14 [get_ports eth_tx_data[0]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[0]]
|
||||
# ## eth:0.tx_data
|
||||
#set_property LOC J14 [get_ports eth_tx_data[1]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[1]]
|
||||
# ## eth:0.tx_data
|
||||
#set_property LOC J13 [get_ports eth_tx_data[2]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[2]]
|
||||
# ## eth:0.tx_data
|
||||
#set_property LOC H17 [get_ports eth_tx_data[3]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[3]]
|
||||
# ## eth:0.col
|
||||
#set_property LOC D17 [get_ports eth_col]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_col]
|
||||
# ## eth:0.crs
|
||||
#set_property LOC G14 [get_ports eth_crs]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_crs]
|
||||
|
||||
set_property INTERNAL_VREF 0.75 [get_iobanks 34]
|
||||
|
||||
|
||||
create_clock -period 10.000 -name clk100 [get_nets clk100]
|
||||
|
||||
#create_clock -name eth_rx_clk -period 40.0 [get_nets eth_rx_clk]
|
||||
|
||||
#create_clock -name eth_tx_clk -period 40.0 [get_nets eth_tx_clk]
|
||||
|
||||
#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -asynchronous
|
||||
|
||||
#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
|
||||
#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
|
||||
|
||||
|
||||
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
|
|
@ -0,0 +1,350 @@
|
|||
## serial:0.tx
|
||||
set_property LOC D10 [get_ports serial_tx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
|
||||
## serial:0.rx
|
||||
set_property LOC A9 [get_ports serial_rx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
|
||||
## clk100:0
|
||||
set_property LOC E3 [get_ports clk100]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk100]
|
||||
## cpu_reset:0
|
||||
set_property LOC C2 [get_ports cpu_reset]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
|
||||
## eth_ref_clk:0
|
||||
#set_property LOC G18 [get_ports eth_ref_clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk]
|
||||
## user_led:0
|
||||
set_property LOC H5 [get_ports user_led0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_led0]
|
||||
## user_led:1
|
||||
set_property LOC J5 [get_ports user_led1]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_led1]
|
||||
## user_led:2
|
||||
set_property LOC T9 [get_ports user_led2]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_led2]
|
||||
## user_led:3
|
||||
set_property LOC T10 [get_ports user_led3]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_led3]
|
||||
## user_sw:0
|
||||
set_property LOC A8 [get_ports user_sw0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_sw0]
|
||||
## user_sw:1
|
||||
set_property LOC C11 [get_ports user_sw1]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_sw1]
|
||||
## user_sw:2
|
||||
set_property LOC C10 [get_ports user_sw2]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_sw2]
|
||||
## user_sw:3
|
||||
set_property LOC A10 [get_ports user_sw3]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_sw3]
|
||||
## user_btn:0
|
||||
set_property LOC D9 [get_ports user_btn0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_btn0]
|
||||
## user_btn:1
|
||||
set_property LOC C9 [get_ports user_btn1]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_btn1]
|
||||
## user_btn:2
|
||||
set_property LOC B9 [get_ports user_btn2]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_btn2]
|
||||
## user_btn:3
|
||||
set_property LOC B8 [get_ports user_btn3]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports user_btn3]
|
||||
## spiflash_1x:0.cs_n
|
||||
#set_property LOC L13 [get_ports spiflash_1x_cs_n]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_cs_n]
|
||||
# ## spiflash_1x:0.mosi
|
||||
#set_property LOC K17 [get_ports spiflash_1x_mosi]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_mosi]
|
||||
# ## spiflash_1x:0.miso
|
||||
#set_property LOC K18 [get_ports spiflash_1x_miso]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_miso]
|
||||
# ## spiflash_1x:0.wp
|
||||
#set_property LOC L14 [get_ports spiflash_1x_wp]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_wp]
|
||||
# ## spiflash_1x:0.hold
|
||||
#set_property LOC M14 [get_ports spiflash_1x_hold]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports spiflash_1x_hold]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC R2 [get_ports ddram_a[0]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[0]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[0]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC M6 [get_ports ddram_a[1]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[1]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[1]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC N4 [get_ports ddram_a[2]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[2]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[2]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC T1 [get_ports ddram_a[3]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[3]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[3]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC N6 [get_ports ddram_a[4]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[4]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[4]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC R7 [get_ports ddram_a[5]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[5]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[5]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC V6 [get_ports ddram_a[6]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[6]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[6]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC U7 [get_ports ddram_a[7]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[7]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[7]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC R8 [get_ports ddram_a[8]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[8]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[8]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC V7 [get_ports ddram_a[9]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[9]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[9]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC R6 [get_ports ddram_a[10]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[10]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[10]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC U6 [get_ports ddram_a[11]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[11]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[11]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC T6 [get_ports ddram_a[12]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[12]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[12]]
|
||||
# ## ddram:0.a
|
||||
#set_property LOC T8 [get_ports ddram_a[13]]
|
||||
#set_property SLEW FAST [get_ports ddram_a[13]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_a[13]]
|
||||
# ## ddram:0.ba
|
||||
#set_property LOC R1 [get_ports ddram_ba[0]]
|
||||
#set_property SLEW FAST [get_ports ddram_ba[0]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[0]]
|
||||
# ## ddram:0.ba
|
||||
#set_property LOC P4 [get_ports ddram_ba[1]]
|
||||
#set_property SLEW FAST [get_ports ddram_ba[1]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[1]]
|
||||
# ## ddram:0.ba
|
||||
#set_property LOC P2 [get_ports ddram_ba[2]]
|
||||
#set_property SLEW FAST [get_ports ddram_ba[2]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_ba[2]]
|
||||
# ## ddram:0.ras_n
|
||||
#set_property LOC P3 [get_ports ddram_ras_n]
|
||||
#set_property SLEW FAST [get_ports ddram_ras_n]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_ras_n]
|
||||
# ## ddram:0.cas_n
|
||||
#set_property LOC M4 [get_ports ddram_cas_n]
|
||||
#set_property SLEW FAST [get_ports ddram_cas_n]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_cas_n]
|
||||
# ## ddram:0.we_n
|
||||
#set_property LOC P5 [get_ports ddram_we_n]
|
||||
#set_property SLEW FAST [get_ports ddram_we_n]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_we_n]
|
||||
# ## ddram:0.cs_n
|
||||
#set_property LOC U8 [get_ports ddram_cs_n]
|
||||
#set_property SLEW FAST [get_ports ddram_cs_n]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_cs_n]
|
||||
# ## ddram:0.dm
|
||||
#set_property LOC L1 [get_ports ddram_dm[0]]
|
||||
#set_property SLEW FAST [get_ports ddram_dm[0]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dm[0]]
|
||||
# ## ddram:0.dm
|
||||
#set_property LOC U1 [get_ports ddram_dm[1]]
|
||||
#set_property SLEW FAST [get_ports ddram_dm[1]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dm[1]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC K5 [get_ports ddram_dq[0]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[0]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[0]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC L3 [get_ports ddram_dq[1]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[1]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[1]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC K3 [get_ports ddram_dq[2]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[2]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[2]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC L6 [get_ports ddram_dq[3]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[3]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[3]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC M3 [get_ports ddram_dq[4]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[4]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[4]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC M1 [get_ports ddram_dq[5]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[5]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[5]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC L4 [get_ports ddram_dq[6]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[6]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[6]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC M2 [get_ports ddram_dq[7]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[7]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[7]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC V4 [get_ports ddram_dq[8]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[8]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[8]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC T5 [get_ports ddram_dq[9]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[9]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[9]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC U4 [get_ports ddram_dq[10]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[10]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[10]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC V5 [get_ports ddram_dq[11]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[11]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[11]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC V1 [get_ports ddram_dq[12]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[12]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[12]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC T3 [get_ports ddram_dq[13]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[13]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[13]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC U3 [get_ports ddram_dq[14]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[14]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[14]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
|
||||
# ## ddram:0.dq
|
||||
#set_property LOC R3 [get_ports ddram_dq[15]]
|
||||
#set_property SLEW FAST [get_ports ddram_dq[15]]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_dq[15]]
|
||||
#set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
|
||||
# ## ddram:0.dqs_p
|
||||
#set_property LOC N2 [get_ports ddram_dqs_p[0]]
|
||||
#set_property SLEW FAST [get_ports ddram_dqs_p[0]]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[0]]
|
||||
# ## ddram:0.dqs_p
|
||||
#set_property LOC U2 [get_ports ddram_dqs_p[1]]
|
||||
#set_property SLEW FAST [get_ports ddram_dqs_p[1]]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[1]]
|
||||
# ## ddram:0.dqs_n
|
||||
#set_property LOC N1 [get_ports ddram_dqs_n[0]]
|
||||
#set_property SLEW FAST [get_ports ddram_dqs_n[0]]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[0]]
|
||||
# ## ddram:0.dqs_n
|
||||
#set_property LOC V2 [get_ports ddram_dqs_n[1]]
|
||||
#set_property SLEW FAST [get_ports ddram_dqs_n[1]]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[1]]
|
||||
# ## ddram:0.clk_p
|
||||
#set_property LOC U9 [get_ports ddram_clk_p]
|
||||
#set_property SLEW FAST [get_ports ddram_clk_p]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_p]
|
||||
# ## ddram:0.clk_n
|
||||
#set_property LOC V9 [get_ports ddram_clk_n]
|
||||
#set_property SLEW FAST [get_ports ddram_clk_n]
|
||||
#set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_n]
|
||||
# ## ddram:0.cke
|
||||
#set_property LOC N5 [get_ports ddram_cke]
|
||||
#set_property SLEW FAST [get_ports ddram_cke]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_cke]
|
||||
# ## ddram:0.odt
|
||||
#set_property LOC R5 [get_ports ddram_odt]
|
||||
#set_property SLEW FAST [get_ports ddram_odt]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_odt]
|
||||
# ## ddram:0.reset_n
|
||||
#set_property LOC K6 [get_ports ddram_reset_n]
|
||||
#set_property SLEW FAST [get_ports ddram_reset_n]
|
||||
#set_property IOSTANDARD SSTL15 [get_ports ddram_reset_n]
|
||||
# ## eth_clocks:0.tx
|
||||
#set_property LOC H16 [get_ports eth_clocks_tx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_tx]
|
||||
# ## eth_clocks:0.rx
|
||||
#set_property LOC F15 [get_ports eth_clocks_rx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_rx]
|
||||
# ## eth:0.rst_n
|
||||
#set_property LOC C16 [get_ports eth_rst_n]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rst_n]
|
||||
# ## eth:0.mdio
|
||||
#set_property LOC K13 [get_ports eth_mdio]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_mdio]
|
||||
# ## eth:0.mdc
|
||||
#set_property LOC F16 [get_ports eth_mdc]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_mdc]
|
||||
# ## eth:0.rx_dv
|
||||
#set_property LOC G16 [get_ports eth_rx_dv]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_dv]
|
||||
# ## eth:0.rx_er
|
||||
#set_property LOC C17 [get_ports eth_rx_er]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_er]
|
||||
# ## eth:0.rx_data
|
||||
#set_property LOC D18 [get_ports eth_rx_data[0]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[0]]
|
||||
# ## eth:0.rx_data
|
||||
#set_property LOC E17 [get_ports eth_rx_data[1]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[1]]
|
||||
# ## eth:0.rx_data
|
||||
#set_property LOC E18 [get_ports eth_rx_data[2]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[2]]
|
||||
# ## eth:0.rx_data
|
||||
#set_property LOC G17 [get_ports eth_rx_data[3]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[3]]
|
||||
# ## eth:0.tx_en
|
||||
#set_property LOC H15 [get_ports eth_tx_en]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_en]
|
||||
# ## eth:0.tx_data
|
||||
#set_property LOC H14 [get_ports eth_tx_data[0]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[0]]
|
||||
# ## eth:0.tx_data
|
||||
#set_property LOC J14 [get_ports eth_tx_data[1]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[1]]
|
||||
# ## eth:0.tx_data
|
||||
#set_property LOC J13 [get_ports eth_tx_data[2]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[2]]
|
||||
# ## eth:0.tx_data
|
||||
#set_property LOC H17 [get_ports eth_tx_data[3]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[3]]
|
||||
# ## eth:0.col
|
||||
#set_property LOC D17 [get_ports eth_col]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_col]
|
||||
# ## eth:0.crs
|
||||
#set_property LOC G14 [get_ports eth_crs]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports eth_crs]
|
||||
|
||||
set_property INTERNAL_VREF 0.750 [get_iobanks 34]
|
||||
|
||||
create_clock -name sys_clk -period 10.0 [get_nets sys_clk]
|
||||
|
||||
create_clock -name clk100 -period 10.0 [get_nets clk100]
|
||||
|
||||
#create_clock -name eth_rx_clk -period 40.0 [get_nets eth_rx_clk]
|
||||
|
||||
#create_clock -name eth_tx_clk -period 40.0 [get_nets eth_tx_clk]
|
||||
|
||||
#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -asynchronous
|
||||
|
||||
#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
|
||||
#set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
|
||||
set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
|
||||
|
||||
set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
|
||||
|
||||
set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#!/bin/sh
|
||||
#Create mcs file for QSPI flash
|
||||
|
||||
cd ./build
|
||||
|
||||
vivado -mode batch -source ../make_mcs_file.tcl -notrace
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
#!/bin/sh
|
||||
|
||||
cd ./build
|
||||
vivado -mode batch -source ../make_mmi_files.tcl -notrace
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
#!/bin/sh
|
||||
|
||||
#cannot rm build because it erase software images that the make file copy there
|
||||
#rm -rf ./build
|
||||
|
||||
mkdir ./build
|
||||
|
||||
cd ./build
|
||||
vivado -mode batch -source ../make_vivado_project.tcl -notrace
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
ROOT=../../..
|
||||
SWBASE=$(ROOT)/src/main/c/murax
|
||||
SOCSW=hello_world
|
||||
SOCMEMSRC=$(SWBASE)/$(SOCSW)/build/$(SOCSW).v
|
||||
SOCMEM=build/soc.mem
|
||||
|
||||
TOP=Murax
|
||||
|
||||
all : build/latest.bit
|
||||
|
||||
../../../$(TOP).v : toplevel.v
|
||||
(cd ../../..; sbt "runMain vexriscv.demo.Murax_arty")
|
||||
|
||||
.PHONY: $(SOCMEMSRC)
|
||||
$(SOCMEMSRC):
|
||||
mkdir -p build
|
||||
make -C $(SWBASE)/$(SOCSW)
|
||||
|
||||
$(SOCMEM) : $(SOCMEMSRC)
|
||||
cp -u $(SOCMEMSRC) $(SOCMEM)
|
||||
|
||||
build/vivado_project/fpga.runs/impl_1/toplevel.bit : toplevel.v arty_a7.xdc ../../../$(TOP).v
|
||||
mkdir -p build
|
||||
./make_vivado_project
|
||||
cp build/vivado_project/fpga.runs/impl_1/toplevel.bit build/latest.bit
|
||||
|
||||
build/soc.mmi: build/vivado_project/fpga.runs/impl_1/toplevel.bit
|
||||
./make_mmi_files
|
||||
|
||||
build/latest_soc_sw.bit : $(SOCMEM) build/soc.mmi
|
||||
rm -f updatemem.jou updatemem.log
|
||||
updatemem -force --meminfo build/soc.mmi --data $(SOCMEM) --bit build/latest.bit --proc dummy --out build/latest_soc_sw.bit
|
||||
cp build/latest_soc_sw.bit build/latest.bit
|
||||
|
||||
build/latest.bit : build/latest_soc_sw.bit
|
||||
|
||||
build/latest.mcs : build/latest.bit
|
||||
./make_mcs_file
|
||||
|
||||
prog : build/latest.bit
|
||||
./write_fpga
|
||||
|
||||
flash : build/latest.mcs
|
||||
./write_flash
|
||||
|
||||
clean-soc-sw:
|
||||
make -C $(SWBASE)/$(SOCSW) clean-all
|
||||
|
||||
soc-sw: clean-soc-sw $(SOCMEM)
|
||||
|
||||
.PHONY: clean
|
||||
clean :
|
||||
rm -rf build
|
||||
mkdir build
|
||||
rm -f updatemem.jou
|
||||
rm -f updatemem.log
|
||||
|
||||
clean-sw: clean-soc-sw
|
||||
|
||||
clean-all : clean clean-sw
|
||||
rm -f ../../../$(TOP).v
|
||||
rm -f ../../../$(TOP).v_*
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
#!/bin/sh
|
||||
|
||||
cd ./build
|
||||
vivado -mode batch -source ../open_vivado_project.tcl -notrace
|
||||
|
|
@ -0,0 +1 @@
|
|||
picocom --baud 115200 --imap lfcrlf /dev/ttyUSB1
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
module toplevel(
|
||||
input wire clk100,
|
||||
input wire cpu_reset,//active low
|
||||
|
||||
input wire tck,
|
||||
input wire tms,
|
||||
input wire tdi,
|
||||
input wire trst,//ignored
|
||||
output reg tdo,
|
||||
|
||||
input wire serial_rx,
|
||||
output wire serial_tx,
|
||||
|
||||
input wire user_sw0,
|
||||
input wire user_sw1,
|
||||
input wire user_sw2,
|
||||
input wire user_sw3,
|
||||
|
||||
input wire user_btn0,
|
||||
input wire user_btn1,
|
||||
input wire user_btn2,
|
||||
input wire user_btn3,
|
||||
|
||||
output wire user_led0,
|
||||
output wire user_led1,
|
||||
output wire user_led2,
|
||||
output wire user_led3
|
||||
);
|
||||
|
||||
wire [31:0] io_gpioA_read;
|
||||
wire [31:0] io_gpioA_write;
|
||||
wire [31:0] io_gpioA_writeEnable;
|
||||
|
||||
wire io_asyncReset = ~cpu_reset;
|
||||
|
||||
assign {user_led3,user_led2,user_led1,user_led0} = io_gpioA_write[3 : 0];
|
||||
assign io_gpioA_read[3:0] = {user_sw3,user_sw2,user_sw1,user_sw0};
|
||||
assign io_gpioA_read[7:4] = {user_btn3,user_btn2,user_btn1,user_btn0};
|
||||
assign io_gpioA_read[11:8] = {tck,tms,tdi,trst};
|
||||
|
||||
reg tesic_tck,tesic_tms,tesic_tdi;
|
||||
wire tesic_tdo;
|
||||
reg soc_tck,soc_tms,soc_tdi;
|
||||
wire soc_tdo;
|
||||
|
||||
always @(*) begin
|
||||
{soc_tck, soc_tms, soc_tdi } = {tck,tms,tdi};
|
||||
tdo = soc_tdo;
|
||||
end
|
||||
|
||||
Murax core (
|
||||
.io_asyncReset(io_asyncReset),
|
||||
.io_mainClk (clk100 ),
|
||||
.io_jtag_tck(soc_tck),
|
||||
.io_jtag_tdi(soc_tdi),
|
||||
.io_jtag_tdo(soc_tdo),
|
||||
.io_jtag_tms(soc_tms),
|
||||
.io_gpioA_read (io_gpioA_read),
|
||||
.io_gpioA_write (io_gpioA_write),
|
||||
.io_gpioA_writeEnable(io_gpioA_writeEnable),
|
||||
.io_uart_txd(serial_tx),
|
||||
.io_uart_rxd(serial_rx)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#!/bin/sh
|
||||
cd ./build
|
||||
vivado -mode batch -source ../write_flash.tcl -notrace
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
#!/bin/sh
|
||||
cd ./build
|
||||
vivado -mode batch -source ../write_fpga.tcl -notrace
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
PROJ_NAME=hello_world
|
||||
DEBUG=no
|
||||
BENCH=no
|
||||
MULDIV=no
|
||||
|
||||
SRCS = $(wildcard src/*.c) \
|
||||
$(wildcard src/*.cpp) \
|
||||
$(wildcard src/*.S)
|
||||
|
||||
OBJDIR = build
|
||||
|
||||
INC =
|
||||
LIBS =
|
||||
LIBSINC = -L$(OBJDIR)
|
||||
LDSCRIPT = ./src/linker.ld
|
||||
|
||||
#include ../../../resources/gcc.mk
|
||||
# Set it to yes if you are using the sifive precompiled GCC pack
|
||||
SIFIVE_GCC_PACK ?= yes
|
||||
|
||||
ifeq ($(SIFIVE_GCC_PACK),yes)
|
||||
RISCV_NAME ?= riscv64-unknown-elf
|
||||
RISCV_PATH ?= /opt/riscv/
|
||||
else
|
||||
RISCV_NAME ?= riscv32-unknown-elf
|
||||
ifeq ($(MULDIV),yes)
|
||||
RISCV_PATH ?= /opt/riscv32im/
|
||||
else
|
||||
RISCV_PATH ?= /opt/riscv32i/
|
||||
endif
|
||||
endif
|
||||
|
||||
MABI=ilp32
|
||||
MARCH := rv32i
|
||||
ifeq ($(MULDIV),yes)
|
||||
MARCH := $(MARCH)m
|
||||
endif
|
||||
ifeq ($(COMPRESSED),yes)
|
||||
MARCH := $(MARCH)ac
|
||||
endif
|
||||
|
||||
CFLAGS += -march=$(MARCH) -mabi=$(MABI) -DNDEBUG
|
||||
LDFLAGS += -march=$(MARCH) -mabi=$(MABI)
|
||||
|
||||
|
||||
|
||||
#include ../../../resources/subproject.mk
|
||||
|
||||
|
||||
ifeq ($(DEBUG),yes)
|
||||
CFLAGS += -g3 -O0
|
||||
endif
|
||||
|
||||
ifeq ($(DEBUG),no)
|
||||
CFLAGS += -g -Os
|
||||
endif
|
||||
|
||||
ifeq ($(BENCH),yes)
|
||||
CFLAGS += -fno-inline
|
||||
endif
|
||||
|
||||
ifeq ($(SIFIVE_GCC_PACK),yes)
|
||||
RISCV_CLIB=$(RISCV_PATH)/$(RISCV_NAME)/lib/$(MARCH)/$(MABI)/
|
||||
else
|
||||
RISCV_CLIB=$(RISCV_PATH)/$(RISCV_NAME)/lib/
|
||||
endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
RISCV_OBJCOPY = $(RISCV_PATH)/bin/$(RISCV_NAME)-objcopy
|
||||
RISCV_OBJDUMP = $(RISCV_PATH)/bin/$(RISCV_NAME)-objdump
|
||||
RISCV_CC=$(RISCV_PATH)/bin/$(RISCV_NAME)-gcc
|
||||
|
||||
CFLAGS += -MD -fstrict-volatile-bitfields -fno-strict-aliasing
|
||||
LDFLAGS += -nostdlib -lgcc -mcmodel=medany -nostartfiles -ffreestanding -Wl,-Bstatic,-T,$(LDSCRIPT),-Map,$(OBJDIR)/$(PROJ_NAME).map,--print-memory-usage
|
||||
#LDFLAGS += -lgcc -lc -lg -nostdlib -lgcc -msave-restore --strip-debug,
|
||||
|
||||
OBJS := $(SRCS)
|
||||
OBJS := $(OBJS:.c=.o)
|
||||
OBJS := $(OBJS:.cpp=.o)
|
||||
OBJS := $(OBJS:.S=.o)
|
||||
OBJS := $(OBJS:..=miaou)
|
||||
OBJS := $(addprefix $(OBJDIR)/,$(OBJS))
|
||||
|
||||
|
||||
all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).v
|
||||
|
||||
$(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR)
|
||||
$(RISCV_CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LIBSINC) $(LIBS)
|
||||
|
||||
%.hex: %.elf
|
||||
$(RISCV_OBJCOPY) -O ihex $^ $@
|
||||
|
||||
%.bin: %.elf
|
||||
$(RISCV_OBJCOPY) -O binary $^ $@
|
||||
|
||||
%.v: %.elf
|
||||
$(RISCV_OBJCOPY) -O verilog $^ $@
|
||||
|
||||
%.asm: %.elf
|
||||
$(RISCV_OBJDUMP) -S -d $^ > $@
|
||||
|
||||
$(OBJDIR)/%.o: %.c
|
||||
mkdir -p $(dir $@)
|
||||
$(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^
|
||||
$(RISCV_CC) -S $(CFLAGS) $(INC) -o $@.disasm $^
|
||||
|
||||
$(OBJDIR)/%.o: %.cpp
|
||||
mkdir -p $(dir $@)
|
||||
$(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^
|
||||
|
||||
$(OBJDIR)/%.o: %.S
|
||||
mkdir -p $(dir $@)
|
||||
$(RISCV_CC) -c $(CFLAGS) -o $@ $^ -D__ASSEMBLY__=1
|
||||
|
||||
$(OBJDIR):
|
||||
mkdir -p $@
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -rf $(OBJDIR)/src
|
||||
rm -f $(OBJDIR)/$(PROJ_NAME).elf
|
||||
rm -f $(OBJDIR)/$(PROJ_NAME).hex
|
||||
rm -f $(OBJDIR)/$(PROJ_NAME).map
|
||||
rm -f $(OBJDIR)/$(PROJ_NAME).v
|
||||
rm -f $(OBJDIR)/$(PROJ_NAME).asm
|
||||
find $(OBJDIR) -type f -name '*.o' -print0 | xargs -0 -r rm
|
||||
find $(OBJDIR) -type f -name '*.d' -print0 | xargs -0 -r rm
|
||||
|
||||
clean-all : clean
|
||||
|
||||
.SECONDARY: $(OBJS)
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
.global crtStart
|
||||
.global main
|
||||
.global irqCallback
|
||||
|
||||
.section .start_jump,"ax",@progbits
|
||||
crtStart:
|
||||
//long jump to allow crtInit to be anywhere
|
||||
//do it always in 12 bytes
|
||||
lui x2, %hi(crtInit)
|
||||
addi x2, x2, %lo(crtInit)
|
||||
jalr x1,x2
|
||||
nop
|
||||
|
||||
.section .text
|
||||
|
||||
.global trap_entry
|
||||
.align 5
|
||||
trap_entry:
|
||||
sw x1, - 1*4(sp)
|
||||
sw x5, - 2*4(sp)
|
||||
sw x6, - 3*4(sp)
|
||||
sw x7, - 4*4(sp)
|
||||
sw x10, - 5*4(sp)
|
||||
sw x11, - 6*4(sp)
|
||||
sw x12, - 7*4(sp)
|
||||
sw x13, - 8*4(sp)
|
||||
sw x14, - 9*4(sp)
|
||||
sw x15, -10*4(sp)
|
||||
sw x16, -11*4(sp)
|
||||
sw x17, -12*4(sp)
|
||||
sw x28, -13*4(sp)
|
||||
sw x29, -14*4(sp)
|
||||
sw x30, -15*4(sp)
|
||||
sw x31, -16*4(sp)
|
||||
addi sp,sp,-16*4
|
||||
call irqCallback
|
||||
lw x1 , 15*4(sp)
|
||||
lw x5, 14*4(sp)
|
||||
lw x6, 13*4(sp)
|
||||
lw x7, 12*4(sp)
|
||||
lw x10, 11*4(sp)
|
||||
lw x11, 10*4(sp)
|
||||
lw x12, 9*4(sp)
|
||||
lw x13, 8*4(sp)
|
||||
lw x14, 7*4(sp)
|
||||
lw x15, 6*4(sp)
|
||||
lw x16, 5*4(sp)
|
||||
lw x17, 4*4(sp)
|
||||
lw x28, 3*4(sp)
|
||||
lw x29, 2*4(sp)
|
||||
lw x30, 1*4(sp)
|
||||
lw x31, 0*4(sp)
|
||||
addi sp,sp,16*4
|
||||
mret
|
||||
.text
|
||||
|
||||
|
||||
crtInit:
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
la sp, _stack_start
|
||||
|
||||
bss_init:
|
||||
la a0, _bss_start
|
||||
la a1, _bss_end
|
||||
bss_loop:
|
||||
beq a0,a1,bss_done
|
||||
sw zero,0(a0)
|
||||
add a0,a0,4
|
||||
j bss_loop
|
||||
bss_done:
|
||||
|
||||
ctors_init:
|
||||
la a0, _ctors_start
|
||||
addi sp,sp,-4
|
||||
ctors_loop:
|
||||
la a1, _ctors_end
|
||||
beq a0,a1,ctors_done
|
||||
lw a3,0(a0)
|
||||
add a0,a0,4
|
||||
sw a0,0(sp)
|
||||
jalr a3
|
||||
lw a0,0(sp)
|
||||
j ctors_loop
|
||||
ctors_done:
|
||||
addi sp,sp,4
|
||||
|
||||
|
||||
li a0, 0x880 //880 enable timer + external interrupts
|
||||
csrw mie,a0
|
||||
li a0, 0x1808 //1808 enable interrupts
|
||||
csrw mstatus,a0
|
||||
|
||||
call main
|
||||
infinitLoop:
|
||||
j infinitLoop
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
#ifndef GPIO_H_
|
||||
#define GPIO_H_
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t INPUT;
|
||||
volatile uint32_t OUTPUT;
|
||||
volatile uint32_t OUTPUT_ENABLE;
|
||||
} Gpio_Reg;
|
||||
|
||||
|
||||
#endif /* GPIO_H_ */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#ifndef INTERRUPTCTRL_H_
|
||||
#define INTERRUPTCTRL_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t PENDINGS;
|
||||
volatile uint32_t MASKS;
|
||||
} InterruptCtrl_Reg;
|
||||
|
||||
static void interruptCtrl_init(InterruptCtrl_Reg* reg){
|
||||
reg->MASKS = 0;
|
||||
reg->PENDINGS = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
#endif /* INTERRUPTCTRL_H_ */
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
This is free and unencumbered software released into the public domain.
|
||||
|
||||
Anyone is free to copy, modify, publish, use, compile, sell, or
|
||||
distribute this software, either in source code form or as a compiled
|
||||
binary, for any purpose, commercial or non-commercial, and by any
|
||||
means.
|
||||
*/
|
||||
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
|
||||
OUTPUT_ARCH(riscv)
|
||||
ENTRY(crtStart)
|
||||
|
||||
MEMORY {
|
||||
RAM (rwx): ORIGIN = 0x80000000, LENGTH = 2k
|
||||
}
|
||||
|
||||
_stack_size = DEFINED(_stack_size) ? _stack_size : 256;
|
||||
_heap_size = DEFINED(_heap_size) ? _heap_size : 0;
|
||||
|
||||
SECTIONS {
|
||||
|
||||
._vector ORIGIN(RAM): {
|
||||
*crt.o(.start_jump);
|
||||
*crt.o(.text);
|
||||
} > RAM
|
||||
|
||||
._user_heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
PROVIDE ( _heap_start = .);
|
||||
. = . + _heap_size;
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( _heap_end = .);
|
||||
} > RAM
|
||||
|
||||
._stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(16);
|
||||
PROVIDE (_stack_end = .);
|
||||
. = . + _stack_size;
|
||||
. = ALIGN(16);
|
||||
PROVIDE (_stack_start = .);
|
||||
} > RAM
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
} > RAM
|
||||
|
||||
.bss (NOLOAD) : {
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_bss_start = .;
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_bss_end = .;
|
||||
} > RAM
|
||||
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} > RAM
|
||||
|
||||
.noinit (NOLOAD) : {
|
||||
. = ALIGN(4);
|
||||
*(.noinit .noinit.*)
|
||||
. = ALIGN(4);
|
||||
} > RAM
|
||||
|
||||
.memory : {
|
||||
*(.text);
|
||||
end = .;
|
||||
} > RAM
|
||||
|
||||
.ctors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_ctors_start = .;
|
||||
KEEP(*(.init_array*))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
. = ALIGN(4);
|
||||
_ctors_end = .;
|
||||
PROVIDE ( END_OF_SW_IMAGE = . );
|
||||
} > RAM
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
//#include "stddefs.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#include "murax.h"
|
||||
|
||||
void print(const char*str){
|
||||
while(*str){
|
||||
uart_write(UART,*str);
|
||||
str++;
|
||||
}
|
||||
}
|
||||
void println(const char*str){
|
||||
print(str);
|
||||
uart_write(UART,'\n');
|
||||
}
|
||||
|
||||
void delay(uint32_t loops){
|
||||
for(int i=0;i<loops;i++){
|
||||
int tmp = GPIO_A->OUTPUT;
|
||||
}
|
||||
}
|
||||
|
||||
void main() {
|
||||
GPIO_A->OUTPUT_ENABLE = 0x0000000F;
|
||||
GPIO_A->OUTPUT = 0x00000001;
|
||||
println("hello world arty a7 v1");
|
||||
const int nleds = 4;
|
||||
const int nloops = 2000000;
|
||||
while(1){
|
||||
for(unsigned int i=0;i<nleds-1;i++){
|
||||
GPIO_A->OUTPUT = 1<<i;
|
||||
delay(nloops);
|
||||
}
|
||||
for(unsigned int i=0;i<nleds-1;i++){
|
||||
GPIO_A->OUTPUT = (1<<(nleds-1))>>i;
|
||||
delay(nloops);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void irqCallback(){
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
#ifndef __MURAX_H__
|
||||
#define __MURAX_H__
|
||||
|
||||
#include "timer.h"
|
||||
#include "prescaler.h"
|
||||
#include "interrupt.h"
|
||||
#include "gpio.h"
|
||||
#include "uart.h"
|
||||
|
||||
#define GPIO_A ((Gpio_Reg*)(0xF0000000))
|
||||
#define TIMER_PRESCALER ((Prescaler_Reg*)0xF0020000)
|
||||
#define TIMER_INTERRUPT ((InterruptCtrl_Reg*)0xF0020010)
|
||||
#define TIMER_A ((Timer_Reg*)0xF0020040)
|
||||
#define TIMER_B ((Timer_Reg*)0xF0020050)
|
||||
#define UART ((Uart_Reg*)(0xF0010000))
|
||||
|
||||
#endif /* __MURAX_H__ */
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#ifndef PRESCALERCTRL_H_
|
||||
#define PRESCALERCTRL_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t LIMIT;
|
||||
} Prescaler_Reg;
|
||||
|
||||
static void prescaler_init(Prescaler_Reg* reg){
|
||||
|
||||
}
|
||||
|
||||
#endif /* PRESCALERCTRL_H_ */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
#ifndef TIMERCTRL_H_
|
||||
#define TIMERCTRL_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t CLEARS_TICKS;
|
||||
volatile uint32_t LIMIT;
|
||||
volatile uint32_t VALUE;
|
||||
} Timer_Reg;
|
||||
|
||||
static void timer_init(Timer_Reg *reg){
|
||||
reg->CLEARS_TICKS = 0;
|
||||
reg->VALUE = 0;
|
||||
}
|
||||
|
||||
|
||||
#endif /* TIMERCTRL_H_ */
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
#ifndef UART_H_
|
||||
#define UART_H_
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
volatile uint32_t DATA;
|
||||
volatile uint32_t STATUS;
|
||||
volatile uint32_t CLOCK_DIVIDER;
|
||||
volatile uint32_t FRAME_CONFIG;
|
||||
} Uart_Reg;
|
||||
|
||||
enum UartParity {NONE = 0,EVEN = 1,ODD = 2};
|
||||
enum UartStop {ONE = 0,TWO = 1};
|
||||
|
||||
typedef struct {
|
||||
uint32_t dataLength;
|
||||
enum UartParity parity;
|
||||
enum UartStop stop;
|
||||
uint32_t clockDivider;
|
||||
} Uart_Config;
|
||||
|
||||
static uint32_t uart_writeAvailability(Uart_Reg *reg){
|
||||
return (reg->STATUS >> 16) & 0xFF;
|
||||
}
|
||||
static uint32_t uart_readOccupancy(Uart_Reg *reg){
|
||||
return reg->STATUS >> 24;
|
||||
}
|
||||
|
||||
static void uart_write(Uart_Reg *reg, uint32_t data){
|
||||
while(uart_writeAvailability(reg) == 0);
|
||||
reg->DATA = data;
|
||||
}
|
||||
|
||||
static void uart_applyConfig(Uart_Reg *reg, Uart_Config *config){
|
||||
reg->CLOCK_DIVIDER = config->clockDivider;
|
||||
reg->FRAME_CONFIG = ((config->dataLength-1) << 0) | (config->parity << 8) | (config->stop << 16);
|
||||
}
|
||||
|
||||
#endif /* UART_H_ */
|
||||
|
||||
|
||||
|
|
@ -477,3 +477,10 @@ object MuraxWithRamInit{
|
|||
SpinalVerilog(Murax(MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")))
|
||||
}
|
||||
}
|
||||
|
||||
object Murax_arty{
|
||||
def main(args: Array[String]) {
|
||||
val hex = "src/main/c/murax/hello_world/build/hello_world.hex"
|
||||
SpinalVerilog(Murax(MuraxConfig.default(false).copy(coreFrequency = 100 MHz,onChipRamSize = 32 kB, onChipRamHexFile = hex)))
|
||||
}
|
||||
}
|
||||
|
|
|
|||
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Reference in New Issue