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VexRiscv
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Fix typo

This commit is contained in:
Dolu1990 2020-06-04 10:11:30 +02:00
parent 89c13bedbd
commit 97c2dc270c
1 changed files with 96 additions and 95 deletions
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189
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexMpCluster.scala
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@ -160,76 +160,76 @@ object VexRiscvLitexSmpMpClusterGen extends App {
object VexRiscvLitexSmpMpClusterOpenSbi extends App{ object VexRiscvLitexSmpMpClusterOpenSbi extends App{
import spinal.core.sim._ import spinal.core.sim._
val simConfig = SimConfig val simConfig = SimConfig
simConfig.withWave simConfig.withWave
simConfig.withFstWave simConfig.withFstWave
simConfig.allOptimisation simConfig.allOptimisation
val cpuCount = 2 val cpuCount = 2
def parameter = VexRiscvLitexSmpMpClusterParameter( def parameter = VexRiscvLitexSmpMpClusterParameter(
cluster = VexRiscvSmpClusterParameter( cluster = VexRiscvSmpClusterParameter(
cpuConfigs = List.tabulate(cpuCount) { hartId => cpuConfigs = List.tabulate(cpuCount) { hartId =>
vexRiscvConfig( vexRiscvConfig(
hartId = hartId, hartId = hartId,
ioRange = address => address(31 downto 28) === 0xF, ioRange = address => address(31 downto 28) === 0xF,
resetVector = 0x80000000l resetVector = 0x80000000l
) )
} }
), ),
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128), liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
liteDramMapping = SizeMapping(0x80000000l, 0x70000000l) liteDramMapping = SizeMapping(0x80000000l, 0x70000000l)
)
def dutGen = {
val top = VexRiscvLitexSmpMpCluster(
p = parameter,
debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
) )
top.rework{
top.io.clint.setAsDirectionLess.allowDirectionLessIo
top.io.peripheral.setAsDirectionLess.allowDirectionLessIo.simPublic()
def dutGen = { val hit = (top.io.peripheral.ADR <<2 >= 0xF0010000l && top.io.peripheral.ADR<<2 < 0xF0020000l)
val top = VexRiscvLitexSmpMpCluster( top.io.clint.CYC := top.io.peripheral.CYC && hit
p = parameter, top.io.clint.STB := top.io.peripheral.STB
debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")) top.io.clint.WE := top.io.peripheral.WE
) top.io.clint.ADR := top.io.peripheral.ADR.resized
top.rework{ top.io.clint.DAT_MOSI := top.io.peripheral.DAT_MOSI
top.io.clint.setAsDirectionLess.allowDirectionLessIo top.io.peripheral.DAT_MISO := top.io.clint.DAT_MISO
top.io.peripheral.setAsDirectionLess.allowDirectionLessIo.simPublic() top.io.peripheral.ACK := top.io.peripheral.CYC && (!hit || top.io.clint.ACK)
top.io.peripheral.ERR := False
val hit = (top.io.peripheral.ADR <<2 >= 0xF0010000l && top.io.peripheral.ADR<<2 < 0xF0020000l)
top.io.clint.CYC := top.io.peripheral.CYC && hit
top.io.clint.STB := top.io.peripheral.STB
top.io.clint.WE := top.io.peripheral.WE
top.io.clint.ADR := top.io.peripheral.ADR.resized
top.io.clint.DAT_MOSI := top.io.peripheral.DAT_MOSI
top.io.peripheral.DAT_MISO := top.io.clint.DAT_MISO
top.io.peripheral.ACK := top.io.peripheral.CYC && (!hit || top.io.clint.ACK)
top.io.peripheral.ERR := False
// top.dMemBridge.unburstified.cmd.simPublic() // top.dMemBridge.unburstified.cmd.simPublic()
}
top
} }
simConfig.compile(dutGen).doSimUntilVoid(seed = 42){dut => top
dut.clockDomain.forkStimulus(10) }
fork { simConfig.compile(dutGen).doSimUntilVoid(seed = 42){dut =>
dut.debugClockDomain.resetSim #= false dut.clockDomain.forkStimulus(10)
sleep (0) fork {
dut.debugClockDomain.resetSim #= true dut.debugClockDomain.resetSim #= false
sleep (10) sleep (0)
dut.debugClockDomain.resetSim #= false dut.debugClockDomain.resetSim #= true
} sleep (10)
dut.debugClockDomain.resetSim #= false
}
val ram = SparseMemory() val ram = SparseMemory()
ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin") ram.loadBin(0x80000000l, "../opensbi/build/platform/spinal/vexriscv/sim/smp/firmware/fw_jump.bin")
ram.loadBin(0xC0000000l, "../buildroot/output/images/Image") ram.loadBin(0xC0000000l, "../buildroot/output/images/Image")
ram.loadBin(0xC1000000l, "../buildroot/output/images/dtb") ram.loadBin(0xC1000000l, "../buildroot/output/images/dtb")
ram.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio") ram.loadBin(0xC2000000l, "../buildroot/output/images/rootfs.cpio")
for(id <- 0 until cpuCount) { for(id <- 0 until cpuCount) {
dut.io.iMem(id).simSlave(ram, dut.clockDomain) dut.io.iMem(id).simSlave(ram, dut.clockDomain)
dut.io.dMem(id).simSlave(ram, dut.clockDomain) dut.io.dMem(id).simSlave(ram, dut.clockDomain)
} }
dut.io.externalInterrupts #= 0 dut.io.externalInterrupts #= 0
dut.io.externalSupervisorInterrupts #= 0 dut.io.externalSupervisorInterrupts #= 0
// val stdin = mutable.Queue[Byte]() // val stdin = mutable.Queue[Byte]()
// def stdInPush(str : String) = stdin ++= str.toCharArray.map(_.toByte) // def stdInPush(str : String) = stdin ++= str.toCharArray.map(_.toByte)
@ -248,43 +248,44 @@ object VexRiscvLitexSmpMpClusterOpenSbi extends App{
// printf("\n** uptime **") // printf("\n** uptime **")
// } // }
// } // }
dut.clockDomain.onFallingEdges{ dut.clockDomain.onFallingEdges {
if(dut.io.peripheral.CYC.toBoolean){ if (dut.io.peripheral.CYC.toBoolean) {
(dut.io.peripheral.ADR.toLong << 2) match { (dut.io.peripheral.ADR.toLong << 2) match {
case 0xF0000000l => print(dut.io.peripheral.DAT_MOSI.toLong.toChar) case 0xF0000000l => print(dut.io.peripheral.DAT_MOSI.toLong.toChar)
case 0xF0000004l => dut.io.peripheral.DAT_MISO #= (if(System.in.available() != 0) System.in.read() else 0xFFFFFFFFl) case 0xF0000004l => dut.io.peripheral.DAT_MISO #= (if (System.in.available() != 0) System.in.read() else 0xFFFFFFFFl)
// case 0xF0000004l => { // case 0xF0000004l => {
// val c = if(stdin.nonEmpty) { // val c = if(stdin.nonEmpty) {
// stdin.dequeue().toInt & 0xFF // stdin.dequeue().toInt & 0xFF
// } else { // } else {
// 0xFFFFFFFFl // 0xFFFFFFFFl
// } // }
// dut.io.peripheral.DAT_MISO #= c // dut.io.peripheral.DAT_MISO #= c
// } // }
// case _ => // case _ =>
// } // }
// println(f"${dut.io.peripheral.ADR.toLong}%x") // println(f"${dut.io.peripheral.ADR.toLong}%x")
}
}
fork{
val at = 0
val duration = 0
while(simTime() < at*1000000l) {
disableSimWave()
sleep(100000 * 10)
enableSimWave()
sleep( 200 * 10)
}
println("\n\n********************")
sleep(duration*1000000l)
println("********************\n\n")
while(true) {
disableSimWave()
sleep(100000 * 10)
enableSimWave()
sleep( 400 * 10)
} }
} }
} }
fork{
val at = 0
val duration = 0
while(simTime() < at*1000000l) {
disableSimWave()
sleep(100000 * 10)
enableSimWave()
sleep( 200 * 10)
}
println("\n\n********************")
sleep(duration*1000000l)
println("********************\n\n")
while(true) {
disableSimWave()
sleep(100000 * 10)
enableSimWave()
sleep( 400 * 10)
}
}
} }
}