SpinalHDL 1.1.2

Add Murax setup with Mul Div Barriel

build.sbt

@@ -9,8 +9,8 @@ scalaVersion := "2.11.6"
 EclipseKeys.withSource := true
 
 libraryDependencies ++= Seq(
-  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.1",
-  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.1",
+  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.1.2",
+  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.1.2",
   "org.yaml" % "snakeyaml" % "1.8"
 )
 

src/main/scala/vexriscv/demo/Murax.scala

@@ -301,6 +301,25 @@ object MuraxDhrystoneReady{
   }
 }
 
+object MuraxDhrystoneReadyMulDivStatic{
+  def main(args: Array[String]) {
+    SpinalVerilog({
+      val config = MuraxConfig.fast.copy(onChipRamSize = 256 kB)
+      config.cpuPlugins += new MulPlugin
+      config.cpuPlugins += new DivPlugin
+      config.cpuPlugins.remove(config.cpuPlugins.indexWhere(_.isInstanceOf[BranchPlugin]))
+      config.cpuPlugins +=new BranchPlugin(
+        earlyBranch = false,
+        catchAddressMisaligned = false,
+        prediction = STATIC
+      )
+      config.cpuPlugins.remove(config.cpuPlugins.indexWhere(_.isInstanceOf[LightShifterPlugin]))
+      config.cpuPlugins += new FullBarrielShifterPlugin
+      Murax(config)
+    })
+  }
+}
+
 //Will blink led and echo UART RX to UART TX   (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
 object MuraxWithRamInit{
   def main(args: Array[String]) {

src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala

@@ -43,15 +43,7 @@ case class Masked(value : BigInt,care : BigInt){
 class DecoderSimplePlugin(catchIllegalInstruction : Boolean, forceLegalInstructionComputation : Boolean = false) extends Plugin[VexRiscv] with DecoderService {
   override def add(encoding: Seq[(MaskedLiteral, Seq[(Stageable[_ <: BaseType], Any)])]): Unit = encoding.foreach(e => this.add(e._1,e._2))
   override def add(key: MaskedLiteral, values: Seq[(Stageable[_ <: BaseType], Any)]): Unit = {
-//    val instructionModel = encodings.getOrElseUpdate(key,ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]())
-    val instructionModel = encodings.find(x => x._1.careAbout == key.careAbout && x._1.width == key.width && x._1.value == key.value) match {
-      case Some(x) => x._2
-      case _ => {
-        val model = ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]()
-        encodings.put(key, model)
-        model
-      }
-    }
+    val instructionModel = encodings.getOrElseUpdate(key,ArrayBuffer[(Stageable[_ <: BaseType], BaseType)]())
     values.map{case (a,b) => {
       assert(!instructionModel.contains(a), s"Over specification of $a")
       val value = b match {