Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add missing full config for the iBus

This commit is contained in:
Dolu1990 2017-11-21 00:09:02 +01:00
parent ce6fd6d0aa
commit 9b9bbaa4ad
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
View File

@ -141,13 +141,13 @@ object VexRiscvAxi4WithIntegratedJtag{
for (plugin <- cpuConfig.plugins) plugin match {
case plugin: IBusSimplePlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAxi4ReadOnly())
iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
.setName("iBusAxi")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
}
case plugin: IBusCachedPlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAxi4ReadOnly())
iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
.setName("iBusAxi")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
}