Merge branch 'master' into dev

2022-02-17 16:27:26 +01:00 · 2022-02-17 16:27:26 +01:00 · 9d3b83366c
parent e4fde184d9 36f57d5eb7
commit 9d3b83366c
1 changed files with 0 additions and 3 deletions
--- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
@ -518,9 +518,6 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
        }

      }
-
-
-      if(rspStage != execute) assert(!(dBus.rsp.ready && input(MEMORY_ENABLE) && arbitration.isValid && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
    }

    //Reformat read responses, REGFILE_WRITE_DATA overriding