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VexRiscv
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Merge branch 'master' into dev

This commit is contained in:
Dolu1990 2022-02-17 16:27:26 +01:00
parent e4fde184d9 36f57d5eb7
commit 9d3b83366c
1 changed files with 0 additions and 3 deletions
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3
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -518,9 +518,6 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
} }
} }
if(rspStage != execute) assert(!(dBus.rsp.ready && input(MEMORY_ENABLE) && arbitration.isValid && arbitration.isStuck),"DBusSimplePlugin doesn't allow memory stage stall when read happend")
} }
//Reformat read responses, REGFILE_WRITE_DATA overriding //Reformat read responses, REGFILE_WRITE_DATA overriding