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VexRiscv
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Move user mode page fault checkes from iBus/dBus plugin into the MmuPlugin 

SUM was in fact already supported
This commit is contained in:
Charles Papon 2019-04-05 21:34:44 +02:00
parent 82c894932a
commit 9e72971ff0
11 changed files with 7 additions and 15 deletions
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2
src/main/scala/vexriscv/Services.scala
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@ -69,7 +69,7 @@ case class MemoryTranslatorCmd() extends Bundle{
case class MemoryTranslatorRsp() extends Bundle{
val physicalAddress = UInt(32 bits)
val isIoAccess = Bool
val allowRead, allowWrite, allowExecute, allowUser = Bool
val allowRead, allowWrite, allowExecute = Bool
val exception = Bool
val refilling = Bool
}

1
src/main/scala/vexriscv/demo/Linux.scala
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@ -89,7 +89,6 @@ https://github.com/riscv/riscv-qemu/wiki#build-and-install
//TODO have to check, look like supervisor can't get interrupt if the machine mod didn't delegated it, have to check exactly
//TODO IBus cached and uncached, do not allow supervisor if it's a user page ? io.cpu.fetch.mmuException
object LinuxGen {
def configFull(litex : Boolean, withMmu : Boolean) = {
val config = VexRiscvConfig(

2
src/main/scala/vexriscv/ip/DataCache.scala
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@ -488,7 +488,7 @@ class DataCache(p : DataCacheConfig) extends Component{
io.cpu.redo := False
io.cpu.writeBack.accessError := False
io.cpu.writeBack.mmuException := io.cpu.writeBack.isValid && (if(catchIllegal) mmuRsp.exception || (!mmuRsp.allowWrite && request.wr) || (!mmuRsp.allowRead && !request.wr) || (!mmuRsp.allowUser && io.cpu.writeBack.isUser) else False)
io.cpu.writeBack.mmuException := io.cpu.writeBack.isValid && (if(catchIllegal) mmuRsp.exception || (!mmuRsp.allowWrite && request.wr) || (!mmuRsp.allowRead && !request.wr) else False)
io.cpu.writeBack.unalignedAccess := io.cpu.writeBack.isValid && (if(catchUnaligned) ((request.size === 2 && mmuRsp.physicalAddress(1 downto 0) =/= 0) || (request.size === 1 && mmuRsp.physicalAddress(0 downto 0) =/= 0)) else False)
io.cpu.writeBack.isWrite := request.wr

4
src/main/scala/vexriscv/ip/InstructionCache.scala
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@ -411,7 +411,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
io.cpu.fetch.cacheMiss := !hit.valid
io.cpu.fetch.error := hit.error
io.cpu.fetch.mmuRefilling := mmuRsp.refilling
io.cpu.fetch.mmuException := !mmuRsp.refilling && (mmuRsp.exception || !mmuRsp.allowExecute || (!mmuRsp.allowUser && io.cpu.fetch.isUser))
io.cpu.fetch.mmuException := !mmuRsp.refilling && (mmuRsp.exception || !mmuRsp.allowExecute)
})
}
@ -441,7 +441,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
io.cpu.decode.cacheMiss := !hit.valid
io.cpu.decode.error := hit.error
io.cpu.decode.mmuRefilling := mmuRsp.refilling
io.cpu.decode.mmuException := !mmuRsp.refilling && (mmuRsp.exception || !mmuRsp.allowExecute || (!mmuRsp.allowUser && io.cpu.decode.isUser))
io.cpu.decode.mmuException := !mmuRsp.refilling && (mmuRsp.exception || !mmuRsp.allowExecute)
io.cpu.decode.physicalAddress := mmuRsp.physicalAddress
})
}

1
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
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@ -286,7 +286,6 @@ class DBusCachedPlugin(config : DataCacheConfig,
mmuBus.cmd.bypassTranslation setWhen(memory.input(IS_DBUS_SHARING))
cache.io.cpu.memory.isValid setWhen(memory.input(IS_DBUS_SHARING))
cache.io.cpu.memory.mmuBus.rsp.allowUser setWhen(memory.input(IS_DBUS_SHARING))
cache.io.cpu.writeBack.isValid setWhen(writeBack.input(IS_DBUS_SHARING))
dBusAccess.rsp.valid := writeBack.input(IS_DBUS_SHARING) && !cache.io.cpu.writeBack.isWrite && (cache.io.cpu.redo || !cache.io.cpu.writeBack.haltIt)
dBusAccess.rsp.data := cache.io.cpu.writeBack.data

2
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -362,7 +362,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
dBus.cmd.address := mmuBus.rsp.physicalAddress
//do not emit memory request if MMU refilling
insert(MMU_FAULT) := input(MMU_RSP).exception || (!input(MMU_RSP).allowWrite && input(MEMORY_STORE)) || (!input(MMU_RSP).allowRead && !input(MEMORY_STORE)) || (!input(MMU_RSP).allowUser && privilegeService.isUser())
insert(MMU_FAULT) := input(MMU_RSP).exception || (!input(MMU_RSP).allowWrite && input(MEMORY_STORE)) || (!input(MMU_RSP).allowRead && !input(MEMORY_STORE))
skipCmd.setWhen(input(MMU_FAULT) || input(MMU_RSP).refilling)
insert(MMU_RSP) := mmuBus.rsp

1
src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
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@ -236,7 +236,6 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
cache.io.cpu.fetch.mmuBus.rsp.allowExecute := True
cache.io.cpu.fetch.mmuBus.rsp.allowRead := True
cache.io.cpu.fetch.mmuBus.rsp.allowWrite := True
cache.io.cpu.fetch.mmuBus.rsp.allowUser := True
cache.io.cpu.fetch.mmuBus.rsp.isIoAccess := False
cache.io.cpu.fetch.mmuBus.rsp.exception := False
cache.io.cpu.fetch.mmuBus.rsp.refilling := False

2
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
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@ -321,7 +321,7 @@ class IBusSimplePlugin(resetVector : BigInt,
}
if(memoryTranslatorPortConfig != null) {
val privilegeService = pipeline.serviceElse(classOf[PrivilegeService], PrivilegeServiceDefault())
when(stages.last.input.valid && !mmu.joinCtx.refilling && (mmu.joinCtx.exception || !mmu.joinCtx.allowExecute || (!mmu.joinCtx.allowUser && privilegeService.isUser()))){
when(stages.last.input.valid && !mmu.joinCtx.refilling && (mmu.joinCtx.exception || !mmu.joinCtx.allowExecute)){
decodeExceptionPort.code := 12
exceptionDetected := True
}

2
src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala
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@ -112,7 +112,6 @@ class MemoryTranslatorPlugin(tlbSize : Int,
port.bus.rsp.allowRead := cacheLine.allowRead
port.bus.rsp.allowWrite := cacheLine.allowWrite
port.bus.rsp.allowExecute := cacheLine.allowExecute
port.bus.rsp.allowUser := cacheLine.allowUser
???
// port.bus.rsp.hit := cacheHit
// port.stage.arbitration.haltItself setWhen (port.bus.cmd.isValid && !cacheHit && !sharedMiss)
@ -121,7 +120,6 @@ class MemoryTranslatorPlugin(tlbSize : Int,
port.bus.rsp.allowRead := True
port.bus.rsp.allowWrite := True
port.bus.rsp.allowExecute := True
port.bus.rsp.allowUser := True
???
// port.bus.rsp.hit := True
}

4
src/main/scala/vexriscv/plugin/MmuPlugin.scala
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@ -124,15 +124,13 @@ class MmuPlugin(ioRange : UInt => Bool,
port.bus.rsp.allowRead := cacheLine.allowRead || csr.status.mxr && cacheLine.allowExecute
port.bus.rsp.allowWrite := cacheLine.allowWrite
port.bus.rsp.allowExecute := cacheLine.allowExecute
port.bus.rsp.allowUser := cacheLine.allowUser
port.bus.rsp.exception := cacheHit && (cacheLine.exception || cacheLine.allowUser && privilegeService.isSupervisor() && !csr.status.sum)
port.bus.rsp.exception := cacheHit && (cacheLine.exception || cacheLine.allowUser && privilegeService.isSupervisor() && !csr.status.sum || !cacheLine.allowUser && privilegeService.isUser())
port.bus.rsp.refilling := !cacheHit
} otherwise {
port.bus.rsp.physicalAddress := port.bus.cmd.virtualAddress
port.bus.rsp.allowRead := True
port.bus.rsp.allowWrite := True
port.bus.rsp.allowExecute := True
port.bus.rsp.allowUser := True
port.bus.rsp.exception := False
port.bus.rsp.refilling := False
}

1
src/main/scala/vexriscv/plugin/StaticMemoryTranslatorPlugin.scala
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@ -31,7 +31,6 @@ class StaticMemoryTranslatorPlugin(ioRange : UInt => Bool) extends Plugin[VexRis
port.bus.rsp.allowRead := True
port.bus.rsp.allowWrite := True
port.bus.rsp.allowExecute := True
port.bus.rsp.allowUser := True
port.bus.rsp.isIoAccess := ioRange(port.bus.rsp.physicalAddress)
port.bus.rsp.exception := False
port.bus.rsp.refilling := False