IBusFetcher disable pcRegReusedForSecondStage when using fetch prediction.
Fix some fetch flush DYNAMIC_PREDICTION start to work again
This commit is contained in:
Charles Papon
parent
8be50b8e3d
commit
9e75e2cb58
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@ -16,7 +16,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val decodePcGen : Boolean,
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val compressedGen : Boolean,
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val cmdToRspStageCount : Int,
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val pcRegReusedForSecondStage : Boolean,
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val allowPcRegReusedForSecondStage : Boolean,
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val injectorReadyCutGen : Boolean,
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val prediction : BranchPrediction,
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val historyRamSizeLog2 : Int,
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@ -43,7 +43,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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injectionPort = Stream(Bits(32 bits))
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injectionPort
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}
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def pcRegReusedForSecondStage = allowPcRegReusedForSecondStage && prediction != DYNAMIC_TARGET
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var predictionJumpInterface : Flow[UInt] = null
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override def haltIt(): Unit = fetcherHalt := True
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@ -68,19 +68,19 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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pipeline(RVC_GEN) = compressedGen
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// prediction match {
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// case NONE =>
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// case STATIC | DYNAMIC => {
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// predictionJumpInterface = createJumpInterface(pipeline.decode)
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// decodePrediction = pipeline.service(classOf[PredictionInterface]).askDecodePrediction()
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// }
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// case DYNAMIC_TARGET => {
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// fetchPrediction = pipeline.service(classOf[PredictionInterface]).askFetchPrediction()
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// if(compressedGen && cmdToRspStageCount > 1){
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// dynamicTargetFailureCorrection = createJumpInterface(pipeline.decode)
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// }
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// }
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// }
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prediction match {
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case NONE =>
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case STATIC | DYNAMIC => {
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predictionJumpInterface = createJumpInterface(pipeline.decode)
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decodePrediction = pipeline.service(classOf[PredictionInterface]).askDecodePrediction()
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}
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case DYNAMIC_TARGET => {
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fetchPrediction = pipeline.service(classOf[PredictionInterface]).askFetchPrediction()
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if(compressedGen && cmdToRspStageCount > 1){
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dynamicTargetFailureCorrection = createJumpInterface(pipeline.decode)
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}
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}
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}
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pcValids = Vec(Bool, pipeline.stages.size)
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}
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@ -131,7 +131,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val booted = RegNext(True) init (False)
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val inc = RegInit(False) clearWhen(corrected || pcRegPropagate) setWhen(output.fire) clearWhen(!output.valid && output.ready)
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val pc = pcReg + (inc ## B"00").asUInt
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// val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
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val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
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val redo = fetchRedoGen generate Flow(UInt(32 bits))
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if(compressedGen) when(inc) {
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@ -142,12 +142,12 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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corrected := True
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pc := redo.payload
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}
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// if(predictionPcLoad != null) {
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// when(predictionPcLoad.valid) {
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// corrected := True
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// pc := predictionPcLoad.payload
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// }
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// }
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if(predictionPcLoad != null) {
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when(predictionPcLoad.valid) {
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corrected := True
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pc := predictionPcLoad.payload
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}
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}
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when(jump.pcLoad.valid) {
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corrected := True
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pc := jump.pcLoad.payload
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@ -178,12 +178,12 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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pcReg := pcPlus
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}
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// val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
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// if(prediction == DYNAMIC_TARGET) {
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// when(predictionPcLoad.valid) {
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// pcReg := predictionPcLoad.payload
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// }
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// }
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val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits)))
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if(prediction == DYNAMIC_TARGET) {
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when(predictionPcLoad.valid) {
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pcReg := predictionPcLoad.payload
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}
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}
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//application of the selected jump request
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when(jump.pcLoad.valid && (!decode.arbitration.isStuck || decode.arbitration.isRemoved)) {
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@ -205,26 +205,25 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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val input = Stream(UInt(32 bits))
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val output = Stream(UInt(32 bits))
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val halt = Bool()
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val inputSample = Bool()
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val flush = Bool()
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})
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stages(0).input << fetchPc.output
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stages(0).inputSample := True
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for(s <- stages) {
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s.halt := False
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s.output << s.input.haltWhen(s.halt)
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}
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stages.head.flush := getFlushAt(IBUS_RSP, stages.head == stages.last) || fetchFlush
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stages.head.flush := False //getFlushAt(IBUS_RSP, stages.head == stages.last) || fetchFlush
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for((s,sNext) <- (stages, stages.tail).zipped) {
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val discardInputOnFlush = s != stages.head
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sNext.flush := getFlushAt(IBUS_RSP, sNext == stages.last) || fetchFlush
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if(s == stages.head && pcRegReusedForSecondStage) {
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sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(sNext.flush, s != stages.head, collapsBubble = false))
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sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(sNext.flush, false, collapsBubble = false, flushInput = s.flush))
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sNext.input.payload := fetchPc.pcReg
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fetchPc.pcRegPropagate setWhen(sNext.input.ready)
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} else {
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sNext.input << s.output.m2sPipeWithFlush(sNext.flush, s != stages.head, collapsBubble = false)
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sNext.input << s.output.m2sPipeWithFlush(sNext.flush, false, collapsBubble = false, flushInput = s.flush)
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}
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}
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@ -234,7 +233,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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}
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val decompressor = ifGen(decodePcGen)(new Area{
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def input = iBusRsp.output
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val input = iBusRsp.output.clearValidWhen(iBusRsp.stages.last.flush)
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val output = Stream(FetchRsp())
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val flush = getFlushAt(DECOMPRESSOR)
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@ -285,7 +284,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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}
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val decodeInput = (if (injectorStage) {
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val flushStage = getFlushAt(INJECTOR_M2S)
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val decodeInput = inputBeforeStage.m2sPipeWithFlush(flushStage, collapsBubble = false)
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val decodeInput = inputBeforeStage.m2sPipeWithFlush(flushStage, false, collapsBubble = false, flushInput = fetcherflushIt)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeStage.rsp.inst)
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iBusRsp.readyForError.clearWhen(decodeInput.valid) //Can't emit error when there is a instruction pending in the injector stage buffer
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incomingInstruction setWhen (decodeInput.valid)
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@ -397,11 +396,11 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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else
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decode.input(PC) + 4)
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// if(decodePc != null && decodePc.predictionPcLoad != null){
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// when(decodePc.predictionPcLoad.valid){
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// decode.insert(FORMAL_PC_NEXT) := decodePc.predictionPcLoad.payload
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// }
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// }
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if(decodePc != null && decodePc.predictionPcLoad != null){
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when(decodePc.predictionPcLoad.valid){
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decode.insert(FORMAL_PC_NEXT) := decodePc.predictionPcLoad.payload
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}
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}
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jumpInfos.foreach(info => {
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when(info.interface.valid) {
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@ -425,182 +424,181 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
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(ifGen(compressedGen)(decompressorContext), injectorContextWire)
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}
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// val predictor = prediction match {
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// case NONE =>
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// case STATIC | DYNAMIC => {
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// def historyWidth = 2
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// val dynamic = ifGen(prediction == DYNAMIC) (new Area {
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// case class BranchPredictorLine() extends Bundle{
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// val history = SInt(historyWidth bits)
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// }
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//
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// val historyCache = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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// val historyWrite = historyCache.writePort
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// val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready)
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// val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(0).input.payload >> 2).resized
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//
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// case class DynamicContext() extends Bundle{
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// val hazard = Bool
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// val line = BranchPredictorLine()
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// }
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// val fetchContext = DynamicContext()
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// fetchContext.hazard := hazard
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// fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt)
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//
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// object PREDICTION_CONTEXT extends Stageable(DynamicContext())
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// decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._2
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// val decodeContextPrediction = decode.input(PREDICTION_CONTEXT).line.history.msb
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//
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// val branchStage = decodePrediction.stage
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// val branchContext = branchStage.input(PREDICTION_CONTEXT)
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// val moreJump = decodePrediction.rsp.wasWrong ^ branchContext.line.history.msb
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//
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// historyWrite.address := branchStage.input(PC)(2, historyRamSizeLog2 bits) + (if(pipeline(RVC_GEN))
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// ((!branchStage.input(IS_RVC) && branchStage.input(PC)(1)) ? U(1) | U(0))
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// else
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// U(0))
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//
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// historyWrite.data.history := branchContext.line.history + (moreJump ? S(-1) | S(1))
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// val sat = (branchContext.line.history === (moreJump ? S(branchContext.line.history.minValue) | S(branchContext.line.history.maxValue)))
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// historyWrite.valid := !branchContext.hazard && branchStage.arbitration.isFiring && branchStage.input(BRANCH_CTRL) === BranchCtrlEnum.B && !sat
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// })
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//
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//
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// val imm = IMM(decode.input(INSTRUCTION))
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//
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// val conditionalBranchPrediction = prediction match {
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// case STATIC => imm.b_sext.msb
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// case DYNAMIC => dynamic.decodeContextPrediction
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// }
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//
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// decodePrediction.cmd.hadBranch := decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL || (decode.input(BRANCH_CTRL) === BranchCtrlEnum.B && conditionalBranchPrediction)
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//
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// val noPredictionOnMissaligned = (!pipeline(RVC_GEN)) generate new Area{
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// val missaligned = decode.input(BRANCH_CTRL).mux(
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// BranchCtrlEnum.JAL -> imm.j_sext(1),
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// default -> imm.b_sext(1)
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// )
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// decodePrediction.cmd.hadBranch clearWhen(missaligned)
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// }
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//
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// //TODO no more fireing depedancies
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// predictionJumpInterface.valid := decode.arbitration.isValid && decodePrediction.cmd.hadBranch //TODO OH Doublon de priorité
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// predictionJumpInterface.payload := decode.input(PC) + ((decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt
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// if(relaxPredictorAddress) KeepAttribute(predictionJumpInterface.payload)
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//
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// when(predictionJumpInterface.valid && decode.arbitration.isFiring){
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// flushIt()
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// }
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// }
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// case DYNAMIC_TARGET => new Area{
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//// assert(!compressedGen || cmdToRspStageCount == 1, "Can't combine DYNAMIC_TARGET and RVC as it could stop the instruction fetch mid-air")
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//
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// case class BranchPredictorLine() extends Bundle{
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// val source = Bits(30 - historyRamSizeLog2 bits)
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// val branchWish = UInt(2 bits)
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// val target = UInt(32 bits)
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// val unaligned = ifGen(compressedGen)(Bool)
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// }
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//
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// val history = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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// val historyWrite = history.writePort
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//
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// val line = history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt)
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// val hit = line.source === (iBusRsp.stages(1).input.payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.stages(1).input.payload(1))) else True)
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//
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// //Avoid stoping instruction fetch in the middle patch
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val predictor = prediction match {
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case NONE =>
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case STATIC | DYNAMIC => {
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def historyWidth = 2
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val dynamic = ifGen(prediction == DYNAMIC) (new Area {
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case class BranchPredictorLine() extends Bundle{
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val history = SInt(historyWidth bits)
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}
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val historyCache = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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val historyWrite = historyCache.writePort
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val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready)
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val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(0).input.payload >> 2).resized
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case class DynamicContext() extends Bundle{
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val hazard = Bool
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val line = BranchPredictorLine()
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}
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val fetchContext = DynamicContext()
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fetchContext.hazard := hazard
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fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt)
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object PREDICTION_CONTEXT extends Stageable(DynamicContext())
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decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._2
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val decodeContextPrediction = decode.input(PREDICTION_CONTEXT).line.history.msb
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val branchStage = decodePrediction.stage
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val branchContext = branchStage.input(PREDICTION_CONTEXT)
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val moreJump = decodePrediction.rsp.wasWrong ^ branchContext.line.history.msb
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historyWrite.address := branchStage.input(PC)(2, historyRamSizeLog2 bits) + (if(pipeline(RVC_GEN))
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((!branchStage.input(IS_RVC) && branchStage.input(PC)(1)) ? U(1) | U(0))
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else
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U(0))
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historyWrite.data.history := branchContext.line.history + (moreJump ? S(-1) | S(1))
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val sat = (branchContext.line.history === (moreJump ? S(branchContext.line.history.minValue) | S(branchContext.line.history.maxValue)))
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historyWrite.valid := !branchContext.hazard && branchStage.arbitration.isFiring && branchStage.input(BRANCH_CTRL) === BranchCtrlEnum.B && !sat
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})
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val imm = IMM(decode.input(INSTRUCTION))
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val conditionalBranchPrediction = prediction match {
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case STATIC => imm.b_sext.msb
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case DYNAMIC => dynamic.decodeContextPrediction
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}
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decodePrediction.cmd.hadBranch := decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL || (decode.input(BRANCH_CTRL) === BranchCtrlEnum.B && conditionalBranchPrediction)
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val noPredictionOnMissaligned = (!pipeline(RVC_GEN)) generate new Area{
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val missaligned = decode.input(BRANCH_CTRL).mux(
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BranchCtrlEnum.JAL -> imm.j_sext(1),
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default -> imm.b_sext(1)
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)
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decodePrediction.cmd.hadBranch clearWhen(missaligned)
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}
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//TODO no more fireing depedancies
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predictionJumpInterface.valid := decode.arbitration.isValid && decodePrediction.cmd.hadBranch //TODO OH Doublon de priorité
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predictionJumpInterface.payload := decode.input(PC) + ((decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt
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if(relaxPredictorAddress) KeepAttribute(predictionJumpInterface.payload)
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when(predictionJumpInterface.valid && decode.arbitration.isFiring){
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flushIt()
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}
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}
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case DYNAMIC_TARGET => new Area{
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// assert(!compressedGen || cmdToRspStageCount == 1, "Can't combine DYNAMIC_TARGET and RVC as it could stop the instruction fetch mid-air")
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case class BranchPredictorLine() extends Bundle{
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val source = Bits(30 - historyRamSizeLog2 bits)
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val branchWish = UInt(2 bits)
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val target = UInt(32 bits)
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val unaligned = ifGen(compressedGen)(Bool)
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}
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val history = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2)
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val historyWrite = history.writePort
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//Avoid write to read hazard
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val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready)
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val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(1).input.payload >> 2).resized
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val line = history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, iBusRsp.stages(0).output.ready)
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val hit = line.source === (iBusRsp.stages(1).input.payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.stages(1).input.payload(1))) else True)
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//Avoid stoping instruction fetch in the middle patch
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// if(compressedGen && cmdToRspStageCount == 1){
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// hit clearWhen(!decompressor.output.valid)
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// }
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//
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// //Avoid write to read hazard
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// val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready)
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// val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(1).input.payload >> 2).resized
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// //TODO improve predictionPcLoad way of doing things
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// fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.stages(1).output.valid //XXX && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))
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// fetchPc.predictionPcLoad.payload := line.target
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//
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// case class PredictionResult() extends Bundle{
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// val hazard = Bool
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// val hit = Bool
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// val line = BranchPredictorLine()
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// }
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//
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// val fetchContext = PredictionResult()
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// fetchContext.hazard := hazard
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// fetchContext.hit := hit
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// fetchContext.line := line
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//
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// val (decompressorContext, injectorContext) = stage1ToInjectorPipe(fetchContext)
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// if(compressedGen) {
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// //prediction hit on the right instruction into words
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// decompressorContext.hit clearWhen(decompressorContext.line.unaligned && (decompressor.bufferValid || (decompressor.isRvc && !decompressor.input.pc(1))))
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//
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// // if(compressedGen) injectorContext.hit clearWhen(decodePc.pcReg(1) =/= injectorContext.line.unaligned)
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//
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// decodePc.predictionPcLoad.valid := injectorContext.line.branchWish.msb && injectorContext.hit && !injectorContext.hazard && injector.decodeInput.fire
|
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// decodePc.predictionPcLoad.payload := injectorContext.line.target
|
||||
//
|
||||
//
|
||||
// when(decompressorContext.line.branchWish.msb && decompressorContext.hit && !decompressorContext.hazard && decompressor.output.fire){
|
||||
// decompressor.bufferValid := False
|
||||
// decompressor.input.ready := True
|
||||
// }
|
||||
// }
|
||||
//
|
||||
// object PREDICTION_CONTEXT extends Stageable(PredictionResult())
|
||||
// pipeline.decode.insert(PREDICTION_CONTEXT) := injectorContext
|
||||
// val branchStage = fetchPrediction.stage
|
||||
// val branchContext = branchStage.input(PREDICTION_CONTEXT)
|
||||
//
|
||||
// fetchPrediction.cmd.hadBranch := branchContext.hit && !branchContext.hazard && branchContext.line.branchWish.msb
|
||||
// fetchPrediction.cmd.targetPc := branchContext.line.target
|
||||
//
|
||||
//
|
||||
// historyWrite.valid := False
|
||||
// historyWrite.address := fetchPrediction.rsp.sourceLastWord(2, historyRamSizeLog2 bits)
|
||||
// historyWrite.data.source := fetchPrediction.rsp.sourceLastWord.asBits >> 2 + historyRamSizeLog2
|
||||
// historyWrite.data.target := fetchPrediction.rsp.finalPc
|
||||
// if(compressedGen) historyWrite.data.unaligned := !fetchPrediction.stage.input(PC)(1) ^ fetchPrediction.stage.input(IS_RVC)
|
||||
//
|
||||
// when(fetchPrediction.rsp.wasRight) {
|
||||
// historyWrite.valid := branchContext.hit
|
||||
// historyWrite.data.branchWish := branchContext.line.branchWish + (branchContext.line.branchWish === 2).asUInt - (branchContext.line.branchWish === 1).asUInt
|
||||
// } otherwise {
|
||||
// when(branchContext.hit) {
|
||||
// historyWrite.valid := True
|
||||
// historyWrite.data.branchWish := branchContext.line.branchWish - (branchContext.line.branchWish.msb).asUInt + (!branchContext.line.branchWish.msb).asUInt
|
||||
// } otherwise {
|
||||
// historyWrite.valid := True
|
||||
// historyWrite.data.branchWish := "10"
|
||||
// }
|
||||
// }
|
||||
//
|
||||
// historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
|
||||
//
|
||||
//
|
||||
//
|
||||
// val predictionFailure = ifGen(compressedGen && cmdToRspStageCount > 1)(new Area{
|
||||
// val predictionBranch = decompressorContext.hit && !decompressorContext.hazard && decompressorContext.line.branchWish(1)
|
||||
// val unalignedWordIssue = decompressor.bufferFill && decompressor.input.rsp.inst(17 downto 16) === 3 && predictionBranch
|
||||
// val decompressorFailure = RegInit(False) setWhen(unalignedWordIssue) clearWhen(fetcherflushIt)
|
||||
// val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready)
|
||||
// val bypassFailure = if(!injectorStage) False else decompressorFailure && !injector.decodeInput.valid
|
||||
//
|
||||
// dynamicTargetFailureCorrection.valid := False
|
||||
// dynamicTargetFailureCorrection.payload := decode.input(PC)
|
||||
// when(injectorFailure || bypassFailure){
|
||||
// historyWrite.valid := True
|
||||
// historyWrite.address := (decode.input(PC) >> 2).resized
|
||||
// historyWrite.data.branchWish := 0
|
||||
//
|
||||
// decode.arbitration.isValid := False
|
||||
// decode.arbitration.flushNext := True
|
||||
// dynamicTargetFailureCorrection.valid := True
|
||||
// }
|
||||
// })
|
||||
// }
|
||||
// }
|
||||
|
||||
fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.stages(1).input.valid
|
||||
fetchPc.predictionPcLoad.payload := line.target
|
||||
|
||||
case class PredictionResult() extends Bundle{
|
||||
val hazard = Bool
|
||||
val hit = Bool
|
||||
val line = BranchPredictorLine()
|
||||
}
|
||||
|
||||
val fetchContext = PredictionResult()
|
||||
fetchContext.hazard := hazard
|
||||
fetchContext.hit := hit
|
||||
fetchContext.line := line
|
||||
|
||||
val (decompressorContext, injectorContext) = stage1ToInjectorPipe(fetchContext)
|
||||
if(compressedGen) {
|
||||
//prediction hit on the right instruction into words
|
||||
decompressorContext.hit clearWhen(decompressorContext.line.unaligned && (decompressor.bufferValid || (decompressor.isRvc && !decompressor.input.pc(1))))
|
||||
|
||||
// if(compressedGen) injectorContext.hit clearWhen(decodePc.pcReg(1) =/= injectorContext.line.unaligned)
|
||||
|
||||
decodePc.predictionPcLoad.valid := injectorContext.line.branchWish.msb && injectorContext.hit && !injectorContext.hazard && injector.decodeInput.fire
|
||||
decodePc.predictionPcLoad.payload := injectorContext.line.target
|
||||
|
||||
|
||||
when(decompressorContext.line.branchWish.msb && decompressorContext.hit && !decompressorContext.hazard && decompressor.output.fire){
|
||||
decompressor.bufferValid := False
|
||||
decompressor.input.ready := True
|
||||
}
|
||||
}
|
||||
|
||||
object PREDICTION_CONTEXT extends Stageable(PredictionResult())
|
||||
pipeline.decode.insert(PREDICTION_CONTEXT) := injectorContext
|
||||
val branchStage = fetchPrediction.stage
|
||||
val branchContext = branchStage.input(PREDICTION_CONTEXT)
|
||||
|
||||
fetchPrediction.cmd.hadBranch := branchContext.hit && !branchContext.hazard && branchContext.line.branchWish.msb
|
||||
fetchPrediction.cmd.targetPc := branchContext.line.target
|
||||
|
||||
|
||||
historyWrite.valid := False
|
||||
historyWrite.address := fetchPrediction.rsp.sourceLastWord(2, historyRamSizeLog2 bits)
|
||||
historyWrite.data.source := fetchPrediction.rsp.sourceLastWord.asBits >> 2 + historyRamSizeLog2
|
||||
historyWrite.data.target := fetchPrediction.rsp.finalPc
|
||||
if(compressedGen) historyWrite.data.unaligned := !fetchPrediction.stage.input(PC)(1) ^ fetchPrediction.stage.input(IS_RVC)
|
||||
|
||||
when(fetchPrediction.rsp.wasRight) {
|
||||
historyWrite.valid := branchContext.hit
|
||||
historyWrite.data.branchWish := branchContext.line.branchWish + (branchContext.line.branchWish === 2).asUInt - (branchContext.line.branchWish === 1).asUInt
|
||||
} otherwise {
|
||||
when(branchContext.hit) {
|
||||
historyWrite.valid := True
|
||||
historyWrite.data.branchWish := branchContext.line.branchWish - (branchContext.line.branchWish.msb).asUInt + (!branchContext.line.branchWish.msb).asUInt
|
||||
} otherwise {
|
||||
historyWrite.valid := True
|
||||
historyWrite.data.branchWish := "10"
|
||||
}
|
||||
}
|
||||
|
||||
historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
|
||||
|
||||
|
||||
|
||||
val predictionFailure = ifGen(compressedGen && cmdToRspStageCount > 1)(new Area{
|
||||
val predictionBranch = decompressorContext.hit && !decompressorContext.hazard && decompressorContext.line.branchWish(1)
|
||||
val unalignedWordIssue = decompressor.bufferFill && decompressor.input.rsp.inst(17 downto 16) === 3 && predictionBranch
|
||||
val decompressorFailure = RegInit(False) setWhen(unalignedWordIssue) clearWhen(fetcherflushIt)
|
||||
val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready)
|
||||
val bypassFailure = if(!injectorStage) False else decompressorFailure && !injector.decodeInput.valid
|
||||
|
||||
dynamicTargetFailureCorrection.valid := False
|
||||
dynamicTargetFailureCorrection.payload := decode.input(PC)
|
||||
when(injectorFailure || bypassFailure){
|
||||
historyWrite.valid := True
|
||||
historyWrite.address := (decode.input(PC) >> 2).resized
|
||||
historyWrite.data.branchWish := 0
|
||||
|
||||
decode.arbitration.isValid := False
|
||||
decode.arbitration.flushNext := True
|
||||
dynamicTargetFailureCorrection.valid := True
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
def stageXToIBusRsp[T <: Data](stage : Any, input : T): (T) ={
|
||||
iBusRsp.stages.dropWhile(_ != stage).tail.foldLeft(input)((data,stage) => RegNextWhen(data, stage.output.ready))
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
|
|||
decodePcGen = compressedGen,
|
||||
compressedGen = compressedGen,
|
||||
cmdToRspStageCount = (if(config.twoCycleCache) 2 else 1) + (if(relaxedPcCalculation) 1 else 0),
|
||||
pcRegReusedForSecondStage = true,
|
||||
allowPcRegReusedForSecondStage = true,
|
||||
injectorReadyCutGen = false,
|
||||
prediction = prediction,
|
||||
historyRamSizeLog2 = historyRamSizeLog2,
|
||||
|
|
|
|||
|
|
@ -240,7 +240,7 @@ class IBusSimplePlugin( resetVector : BigInt,
|
|||
decodePcGen = compressedGen,
|
||||
compressedGen = compressedGen,
|
||||
cmdToRspStageCount = busLatencyMin + (if(cmdForkOnSecondStage) 1 else 0),
|
||||
pcRegReusedForSecondStage = !(cmdForkOnSecondStage && cmdForkPersistence),
|
||||
allowPcRegReusedForSecondStage = !(cmdForkOnSecondStage && cmdForkPersistence),
|
||||
injectorReadyCutGen = false,
|
||||
prediction = prediction,
|
||||
historyRamSizeLog2 = historyRamSizeLog2,
|
||||
|
|
|
|||
|
|
@ -122,7 +122,7 @@ object StreamForkVex{
|
|||
|
||||
object StreamVexPimper{
|
||||
implicit class StreamFlushPimper[T <: Data](pimped : Stream[T]){
|
||||
def m2sPipeWithFlush(flush : Bool, discardInput : Boolean = true, collapsBubble : Boolean = true): Stream[T] = {
|
||||
def m2sPipeWithFlush(flush : Bool, discardInput : Boolean = true, collapsBubble : Boolean = true, flushInput : Bool = null): Stream[T] = {
|
||||
val ret = cloneOf(pimped)
|
||||
|
||||
val rValid = RegInit(False)
|
||||
|
|
@ -132,7 +132,10 @@ object StreamVexPimper{
|
|||
pimped.ready := (Bool(collapsBubble) && !ret.valid) || ret.ready
|
||||
|
||||
when(pimped.ready) {
|
||||
rValid := pimped.valid
|
||||
if(flushInput == null)
|
||||
rValid := pimped.valid
|
||||
else
|
||||
rValid := pimped.valid && !flushInput
|
||||
rData := pimped.payload
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue