improve LitexCluster area for single core configuration
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parent
da666ade49
commit
9f62f37538
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@ -22,7 +22,7 @@ import scala.collection.mutable
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import scala.collection.mutable.ArrayBuffer
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import spinal.lib.generator._
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case class VexRiscvSmpClusterParameter( cpuConfigs : Seq[VexRiscvConfig])
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case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig], withExclusiveAndInvalidation : Boolean)
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class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Generator{
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val cpuCount = p.cpuConfigs.size
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@ -44,16 +44,28 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Generator{
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val debugPort = debugBridge.produceIo(debugBridge.logic.jtagBridge.io.ctrl)
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val exclusiveMonitor = BmbExclusiveMonitorGenerator()
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val invalidationMonitor = BmbInvalidateMonitorGenerator()
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interconnect.addConnection(exclusiveMonitor.output, invalidationMonitor.input)
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interconnect.masters(invalidationMonitor.output).withOutOfOrderDecoder()
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val dBusCoherent = BmbBridgeGenerator()
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val dBusNonCoherent = BmbBridgeGenerator()
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val smp = p.withExclusiveAndInvalidation generate new Area{
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val exclusiveMonitor = BmbExclusiveMonitorGenerator()
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interconnect.addConnection(dBusCoherent.bmb, exclusiveMonitor.input)
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val invalidationMonitor = BmbInvalidateMonitorGenerator()
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interconnect.addConnection(exclusiveMonitor.output, invalidationMonitor.input)
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interconnect.addConnection(invalidationMonitor.output, dBusNonCoherent.bmb)
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interconnect.masters(invalidationMonitor.output).withOutOfOrderDecoder()
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}
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val noSmp = !p.withExclusiveAndInvalidation generate new Area{
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interconnect.addConnection(dBusCoherent.bmb, dBusNonCoherent.bmb)
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}
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val cores = for(cpuId <- 0 until cpuCount) yield new Area{
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val cpu = VexRiscvBmbGenerator()
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cpu.config.load(p.cpuConfigs(cpuId))
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interconnect.addConnection(
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cpu.dBus -> List(exclusiveMonitor.input)
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cpu.dBus -> List(dBusCoherent.bmb)
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)
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cpu.enableDebugBmb(
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debugCd = debugCd,
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@ -113,7 +125,8 @@ object VexRiscvSmpClusterGen {
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ioRange : UInt => Bool = (x => x(31 downto 28) === 0xF),
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resetVector : Long = 0x80000000l,
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iBusWidth : Int = 128,
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dBusWidth : Int = 64) = {
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dBusWidth : Int = 64,
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coherency : Boolean = true) = {
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val config = VexRiscvConfig(
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plugins = List(
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@ -167,8 +180,8 @@ object VexRiscvSmpClusterGen {
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catchUnaligned = true,
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withLrSc = true,
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withAmo = true,
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withExclusive = true,
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withInvalidate = true,
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withExclusive = coherency,
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withInvalidate = coherency,
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aggregationWidth = if(dBusWidth == 32) 0 else log2Up(dBusWidth/8)
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// )
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),
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@ -22,11 +22,11 @@ class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexR
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for(core <- cores) interconnect.addConnection(core.cpu.iBus -> List(iArbiter.bmb))
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interconnect.addConnection(
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iArbiter.bmb -> List(iBridge.bmb, peripheralBridge.bmb),
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invalidationMonitor.output -> List(dBridge.bmb, peripheralBridge.bmb)
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iArbiter.bmb -> List(iBridge.bmb, peripheralBridge.bmb),
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dBusNonCoherent.bmb -> List(dBridge.bmb, peripheralBridge.bmb)
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)
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if(p.coherentDma || p.cluster.cpuConfigs.size > 1) interconnect.masters(invalidationMonitor.output).withOutOfOrderDecoder()
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if(p.cluster.withExclusiveAndInvalidation) interconnect.masters(dBusNonCoherent.bmb).withOutOfOrderDecoder()
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dBridge.liteDramParameter.load(p.liteDram)
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iBridge.liteDramParameter.load(p.liteDram)
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@ -41,7 +41,7 @@ class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexR
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dataWidth = p.cluster.cpuConfigs.head.find(classOf[DBusCachedPlugin]).get.config.memDataWidth,
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useSTALL = true
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))
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interconnect.addConnection(bridge.bmb, exclusiveMonitor.input)
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interconnect.addConnection(bridge.bmb, dBusCoherent.bmb)
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}
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// Interconnect pipelining (FMax)
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@ -50,7 +50,7 @@ class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter) extends VexR
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interconnect.setPipelining(core.cpu.iBus)(cmdHalfRate = true, rspValid = true)
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interconnect.setPipelining(iArbiter.bmb)(cmdHalfRate = true, rspValid = true)
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}
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interconnect.setPipelining(invalidationMonitor.output)(cmdValid = true, cmdReady = true, rspValid = true)
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interconnect.setPipelining(dBusNonCoherent.bmb)(cmdValid = true, cmdReady = true, rspValid = true)
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interconnect.setPipelining(peripheralBridge.bmb)(cmdHalfRate = true, rspValid = true)
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}
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@ -74,6 +74,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
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opt[String]("netlist-name") action { (v, c) => netlistName = v }
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}.parse(args))
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val coherency = coherentDma || cpuCount > 1
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def parameter = VexRiscvLitexSmpClusterParameter(
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cluster = VexRiscvSmpClusterParameter(
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cpuConfigs = List.tabulate(cpuCount) { hartId =>
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@ -82,9 +83,11 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
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ioRange = address => address.msb,
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resetVector = 0,
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iBusWidth = iBusWidth,
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dBusWidth = dBusWidth
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dBusWidth = dBusWidth,
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coherency = coherency
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)
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}
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},
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withExclusiveAndInvalidation = coherency
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),
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liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth),
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liteDramMapping = SizeMapping(0x40000000l, 0x40000000l),
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@ -114,7 +117,8 @@ object VexRiscvLitexSmpClusterGen extends App {
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ioRange = address => address.msb,
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resetVector = 0
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)
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}
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},
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withExclusiveAndInvalidation = true
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),
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liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
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liteDramMapping = SizeMapping(0x40000000l, 0x40000000l),
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@ -152,7 +156,8 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
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ioRange = address => address(31 downto 28) === 0xF,
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resetVector = 0x80000000l
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)
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}
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},
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withExclusiveAndInvalidation = true
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),
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liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
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liteDramMapping = SizeMapping(0x80000000l, 0x70000000l),
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@ -7,64 +7,64 @@ import spinal.lib.bus.wishbone.{WishboneConfig, WishboneToBmbGenerator}
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import spinal.lib.sim.SparseMemory
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import vexriscv.demo.smp.VexRiscvSmpClusterGen.vexRiscvConfig
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case class VexRiscvLitexSmpMpClusterParameter( cluster : VexRiscvSmpClusterParameter,
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liteDram : LiteDramNativeParameter,
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liteDramMapping : AddressMapping)
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class VexRiscvLitexSmpMpCluster(p : VexRiscvLitexSmpMpClusterParameter) extends VexRiscvSmpClusterWithPeripherals(p.cluster) {
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val iArbiter = BmbBridgeGenerator()
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val iBridge = BmbToLiteDramGenerator(p.liteDramMapping)
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val dBridge = BmbToLiteDramGenerator(p.liteDramMapping)
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for(core <- cores) interconnect.addConnection(core.cpu.iBus -> List(iArbiter.bmb))
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interconnect.addConnection(
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iArbiter.bmb -> List(iBridge.bmb, peripheralBridge.bmb),
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invalidationMonitor.output -> List(dBridge.bmb, peripheralBridge.bmb)
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)
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interconnect.masters(invalidationMonitor.output).withOutOfOrderDecoder()
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dBridge.liteDramParameter.load(p.liteDram)
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iBridge.liteDramParameter.load(p.liteDram)
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// Interconnect pipelining (FMax)
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for(core <- cores) {
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interconnect.setPipelining(core.cpu.dBus)(cmdValid = true, cmdReady = true, rspValid = true)
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interconnect.setPipelining(core.cpu.iBus)(cmdHalfRate = true, rspValid = true)
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interconnect.setPipelining(iArbiter.bmb)(cmdHalfRate = true, rspValid = true)
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}
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interconnect.setPipelining(invalidationMonitor.output)(cmdValid = true, cmdReady = true, rspValid = true)
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interconnect.setPipelining(peripheralBridge.bmb)(cmdHalfRate = true, rspValid = true)
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}
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object VexRiscvLitexSmpMpClusterGen extends App {
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for(cpuCount <- List(1,2,4,8)) {
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def parameter = VexRiscvLitexSmpMpClusterParameter(
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cluster = VexRiscvSmpClusterParameter(
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cpuConfigs = List.tabulate(cpuCount) { hartId =>
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vexRiscvConfig(
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hartId = hartId,
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ioRange = address => address.msb,
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resetVector = 0
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)
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}
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),
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liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
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liteDramMapping = SizeMapping(0x40000000l, 0x40000000l)
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)
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def dutGen = {
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val toplevel = new VexRiscvLitexSmpMpCluster(
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p = parameter
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).toComponent()
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toplevel
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}
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val genConfig = SpinalConfig().addStandardMemBlackboxing(blackboxByteEnables)
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// genConfig.generateVerilog(Bench.compressIo(dutGen))
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genConfig.generateVerilog(dutGen.setDefinitionName(s"VexRiscvLitexSmpMpCluster_${cpuCount}c"))
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}
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}
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//case class VexRiscvLitexSmpMpClusterParameter( cluster : VexRiscvSmpClusterParameter,
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// liteDram : LiteDramNativeParameter,
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// liteDramMapping : AddressMapping)
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//
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//class VexRiscvLitexSmpMpCluster(p : VexRiscvLitexSmpMpClusterParameter) extends VexRiscvSmpClusterWithPeripherals(p.cluster) {
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// val iArbiter = BmbBridgeGenerator()
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// val iBridge = BmbToLiteDramGenerator(p.liteDramMapping)
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// val dBridge = BmbToLiteDramGenerator(p.liteDramMapping)
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//
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// for(core <- cores) interconnect.addConnection(core.cpu.iBus -> List(iArbiter.bmb))
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// interconnect.addConnection(
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// iArbiter.bmb -> List(iBridge.bmb, peripheralBridge.bmb),
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// invalidationMonitor.output -> List(dBridge.bmb, peripheralBridge.bmb)
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// )
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// interconnect.masters(invalidationMonitor.output).withOutOfOrderDecoder()
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//
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// dBridge.liteDramParameter.load(p.liteDram)
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// iBridge.liteDramParameter.load(p.liteDram)
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//
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// // Interconnect pipelining (FMax)
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// for(core <- cores) {
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// interconnect.setPipelining(core.cpu.dBus)(cmdValid = true, cmdReady = true, rspValid = true)
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// interconnect.setPipelining(core.cpu.iBus)(cmdHalfRate = true, rspValid = true)
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// interconnect.setPipelining(iArbiter.bmb)(cmdHalfRate = true, rspValid = true)
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// }
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// interconnect.setPipelining(invalidationMonitor.output)(cmdValid = true, cmdReady = true, rspValid = true)
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// interconnect.setPipelining(peripheralBridge.bmb)(cmdHalfRate = true, rspValid = true)
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//}
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//
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//
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//object VexRiscvLitexSmpMpClusterGen extends App {
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// for(cpuCount <- List(1,2,4,8)) {
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// def parameter = VexRiscvLitexSmpMpClusterParameter(
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// cluster = VexRiscvSmpClusterParameter(
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// cpuConfigs = List.tabulate(cpuCount) { hartId =>
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// vexRiscvConfig(
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// hartId = hartId,
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// ioRange = address => address.msb,
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// resetVector = 0
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// )
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// }
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// ),
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// liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
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// liteDramMapping = SizeMapping(0x40000000l, 0x40000000l)
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// )
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//
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// def dutGen = {
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// val toplevel = new VexRiscvLitexSmpMpCluster(
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// p = parameter
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// ).toComponent()
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// toplevel
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// }
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//
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// val genConfig = SpinalConfig().addStandardMemBlackboxing(blackboxByteEnables)
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// // genConfig.generateVerilog(Bench.compressIo(dutGen))
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// genConfig.generateVerilog(dutGen.setDefinitionName(s"VexRiscvLitexSmpMpCluster_${cpuCount}c"))
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// }
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//}
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@ -417,7 +417,8 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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val timer = Reg(UInt(log2Up(timeoutCycles)+1 bits)) init(0)
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val timerFull = timer.msb
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val hit = cmd.address(tagRange) === buffer.address(tagRange)
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val canAggregate = cmd.valid && cmd.wr && !cmd.uncached && !cmd.exclusive && !timerFull && !aggregationCounterFull && (!buffer.stream.valid || aggregationEnabled && hit)
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val cmdExclusive = if(p.withExclusive) cmd.exclusive else False
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val canAggregate = cmd.valid && cmd.wr && !cmd.uncached && !cmdExclusive && !timerFull && !aggregationCounterFull && (!buffer.stream.valid || aggregationEnabled && hit)
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val doFlush = cmd.valid && !canAggregate || timerFull || aggregationCounterFull || !aggregationEnabled
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// val canAggregate = False
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// val doFlush = True
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@ -468,7 +469,7 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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buffer.length := (cmd.length << 2) | 3
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if (p.withExclusive) buffer.exclusive := cmd.exclusive
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when(cmd.wr && !cmd.uncached && !cmd.exclusive){
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when(cmd.wr && !cmd.uncached && !cmdExclusive){
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aggregationEnabled := True
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buffer.address(aggregationRange.high downto 0) := 0
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buffer.length := p.memDataBytes-1
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