Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fix non smp regression

This commit is contained in:
Dolu1990 2020-04-06 06:43:28 +02:00
parent ca72a421be
commit a107e45116
2 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/test/cpp/regression/main.cpp
View File

@ -904,7 +904,11 @@ public:
trap(0, 6, address);
} else {
if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
bool hit = lrscReserved && lrscReservedAddress == pAddr;
#ifdef SMP
bool hit = lrscReserved && lrscReservedAddress == pAddr;
#else
bool hit = lrscReserved;
#endif
if(hit){
dWrite(pAddr, 4, i32_rs2);
}

2
src/test/scala/vexriscv/TestIndividualFeatures.scala
View File

@ -716,7 +716,7 @@ class TestIndividualFeatures extends MultithreadedFunSuite {
//Test RTL
val debug = true
val stdCmd = (s"make run REGRESSION_PATH=../../src/test/cpp/regression VEXRISCV_FILE=VexRiscv.v WITH_USER_IO=no REDO=10 TRACE=${if(debug) "yes" else "no"} TRACE_START=1000000000000l FLOW_INFO=no STOP_ON_ERROR=no DHRYSTONE=yes COREMARK=${coremarkRegression} THREAD_COUNT=1 ") + s" SEED=${testSeed} "
val stdCmd = (s"make run REGRESSION_PATH=../../src/test/cpp/regression VEXRISCV_FILE=VexRiscv.v WITH_USER_IO=no REDO=10 TRACE=${if(debug) "yes" else "no"} TRACE_START=1000000000ll FLOW_INFO=no STOP_ON_ERROR=no DHRYSTONE=yes COREMARK=${coremarkRegression} THREAD_COUNT=1 ") + s" SEED=${testSeed} "
val testCmd = stdCmd + (positionsToApply).map(_.testParam).mkString(" ")
println(testCmd)
val str = doCmd(testCmd)