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VexRiscv
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This commit is contained in:
Dolu1990 2023-03-27 09:57:55 +02:00
parent e754c5c3a0
commit a33380894c
1 changed files with 11 additions and 11 deletions
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22
src/main/scala/vexriscv/TestsWorkspace.scala
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@ -144,19 +144,19 @@ object TestsWorkspace {
withDouble = true, withDouble = true,
externalFpu = false, externalFpu = false,
simHalt = true, simHalt = true,
privilegedDebug = true privilegedDebug = false
) )
config.plugins += new EmbeddedRiscvJtag( // config.plugins += new EmbeddedRiscvJtag(
p = DebugTransportModuleParameter( // p = DebugTransportModuleParameter(
addressWidth = 7, // addressWidth = 7,
version = 1, // version = 1,
idle = 7 // idle = 7
), // ),
debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")), // debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")),
withTunneling = false, // withTunneling = false,
withTap = true // withTap = true
) // )
// l.foreach{ // l.foreach{
// case p : EmbeddedRiscvJtag => p.debugCd.load(ClockDomain.current.copy(reset = Bool().setName("debug_reset"))) // case p : EmbeddedRiscvJtag => p.debugCd.load(ClockDomain.current.copy(reset = Bool().setName("debug_reset")))