Fix MMU A and D flag handeling
This commit is contained in:
Dolu1990
parent
344b2d4eda
commit
a40d5f19b2
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@ -281,11 +281,11 @@ class MmuPlugin(ioRange : UInt => Bool,
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when(port.entryToReplace === lineId){
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val superPage = state === State.L1_RSP
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line.valid := True
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line.exception := dBusRsp.exception || (superPage && dBusRsp.pte.PPN0 =/= 0)
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line.exception := dBusRsp.exception || (superPage && dBusRsp.pte.PPN0 =/= 0) || !dBusRsp.pte.A
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line.virtualAddress := vpn
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line.physicalAddress := Vec(dBusRsp.pte.PPN0, dBusRsp.pte.PPN1(9 downto 0))
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line.allowRead := dBusRsp.pte.R
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line.allowWrite := dBusRsp.pte.W
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line.allowWrite := dBusRsp.pte.W && dBusRsp.pte.D
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line.allowExecute := dBusRsp.pte.X
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line.allowUser := dBusRsp.pte.U
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line.superPage := state === State.L1_RSP
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@ -53,13 +53,13 @@ test5: //setup MMU
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la x1, MMU_TABLE_0 + 0x800
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la x2, MMU_TABLE_1
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srli x2, x2, 2
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ori x2, x2, 0x11
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ori x2, x2, 0x1
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sw x2, 0(x1)
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la x1, MMU_TABLE_1 + 0x000*4
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li x2, 0x80000000
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srli x2, x2, 2
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ori x2, x2, 0x0F
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ori x2, x2, 0x0F | 0xC0
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sw x2, 0(x1)
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@ -67,50 +67,50 @@ test5: //setup MMU
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la x1, MMU_TABLE_0 + 0x900
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la x2, MMU_TABLE_2
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srli x2, x2, 2
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ori x2, x2, 0x11
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ori x2, x2, 0x01
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sw x2, 0(x1)
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la x1, MMU_TABLE_2 + 0x00A*4
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la x2, ROM_4
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srli x2, x2, 2
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ori x2, x2, 0x1F
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ori x2, x2, 0x1F | 0xC0
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sw x2, 0(x1)
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la x1, MMU_TABLE_2 + 0x010*4 // Read Only
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la x2, ROM_5
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srli x2, x2, 2
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ori x2, x2, 0x11 + (0x1 << 1)
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ori x2, x2, 0x11 + (0x1 << 1) | 0xC0
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sw x2, 0(x1)
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la x1, MMU_TABLE_2 + 0x011*4 // Read Write
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la x2, ROM_5
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srli x2, x2, 2
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ori x2, x2, 0x11 + (0x3 << 1)
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ori x2, x2, 0x11 + (0x3 << 1) | 0xC0
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sw x2, 0(x1)
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la x1, MMU_TABLE_2 + 0x012*4 // Execute only
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la x2, ROM_5
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srli x2, x2, 2
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ori x2, x2, 0x11 + (0x4 << 1)
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ori x2, x2, 0x11 + (0x4 << 1) | 0xC0
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sw x2, 0(x1)
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la x1, MMU_TABLE_2 + 0x013*4 //Read Execute
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la x2, ROM_5
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srli x2, x2, 2
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ori x2, x2, 0x11 + (0x5 << 1)
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ori x2, x2, 0x11 + (0x5 << 1) | 0xC0
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sw x2, 0(x1)
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la x1, MMU_TABLE_2 + 0x014*4 //no user
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la x2, ROM_5
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srli x2, x2, 2
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ori x2, x2, 0x01 + (0x7 << 1)
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ori x2, x2, 0x01 + (0x7 << 1) | 0xC0
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sw x2, 0(x1)
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li TEST_ID, 5
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la x1, MMU_TABLE_0 + 0xA00
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la x2, ROM_SUPER_0
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srli x2, x2, 2
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ori x2, x2, 0x1F
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ori x2, x2, 0x1F | 0xC0
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sw x2, 0(x1)
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li TEST_ID, 5
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@ -124,7 +124,9 @@ test5: //setup MMU
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srli x1, x1, 12
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li x2, 0x80000000
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or x1, x1, x2
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sfence.vma
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csrw satp, x1
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fence.i
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test6: //read through MMU
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@ -254,8 +256,8 @@ test17: //Test limited write access
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test18: //Test limited execute access
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li TEST_ID, 18
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la x1, test18_end
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li TRAP_OK, 1
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la TRAP_RET, test18_end
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li x2, 0x90012010
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jr x2
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j fail
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@ -305,7 +307,6 @@ test21: //supervisor accessing not user
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bne x1, x2, fail
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li x1, 1 << 18 //clear SUM
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csrc sstatus, x1
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li TRAP_OK, 1
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@ -320,6 +321,7 @@ test21_pass:
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test50: //User mode setup
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li TEST_ID, 50
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li TRAP_OK, 0
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@ -331,10 +333,10 @@ test50: //User mode setup
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//remap code tlb into userspace
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csrr x10, satp
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csrw satp, x0
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la x1, MMU_TABLE_1 + 0x000*4
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li x2, 0x80000000
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la x1, MMU_TABLE_1 + 0x00D*4 //test51
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li x2, 0x8000D000
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srli x2, x2, 2
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ori x2, x2, 0x1F
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ori x2, x2, 0x1F | 0x40
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sw x2, 0(x1)
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csrw satp, x10
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@ -347,83 +349,32 @@ test50: //User mode setup
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sret
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j fail
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test51: //user read/write
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li TEST_ID, 51
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li x1, 0x90011008
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li x2, 0x5B5A5958
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lw x1, 0(x1)
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bne x1, x2, fail
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li x1, 0xA000A324
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li x2, 0xAAEE0008
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sw x2, 0(x1)
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lw x1, 0(x1)
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bne x1, x2, fail
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test52: //user fetch
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li TEST_ID, 52
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la x1, test53
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li x2, 0x90012010
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jr x2
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j fail
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test53: // user fetch page fault
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li TEST_ID, 53
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li TRAP_OK, 1
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la TRAP_RET, test54
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li x1, 0x90014390
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jr x1
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j fail
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test54: //user load page fault
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li TEST_ID, 54
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li TRAP_OK, 1
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la TRAP_RET, test55
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li x1, 0x90014394
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lw x1, 0(x1)
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j fail
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test55: //user store page fault
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li TEST_ID, 55
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li TRAP_OK, 1
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la TRAP_RET, test56
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li x1, 0x90014398
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sw x1, 0(x1)
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j fail
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test56:
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j pass
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fail: //TEST_ID => error code
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li TRAP_OK, 0
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la TRAP_RET, failFence
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ecall
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failFence:
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li x2, 0xF00FFF24
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sw TEST_ID, 0(x2)
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pass:
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li TRAP_OK, 2
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li TRAP_OK, 1
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la TRAP_RET, passFence
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ecall
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passFence:
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li x2, 0xF00FFF20
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sw x0, 0(x2)
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.align 4
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trap:
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beq TRAP_OK, x0, failFence
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beq TRAP_OK, x0, fail
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csrr x1, mcause
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csrr x1, mepc
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csrr x1, mstatus
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csrr x1, mbadaddr
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li x1, 2
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beq TRAP_OK, x1, passFence
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beq TRAP_OK, x1, pass
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csrw mepc, TRAP_RET
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mret
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@ -435,6 +386,7 @@ trap:
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nop
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nop
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.align 12
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MMU_TABLE_0:
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.word 0
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@ -508,19 +460,53 @@ ROM_7:
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.word 0x7B7A7978
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.word 0x7F7E7D7C
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/*
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.align 22
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ROM_SUPER_0:
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.word 0x83828180
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.word 0x87868584
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.word 0x8B8A8988
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.word 0x8F8E8D8C
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.align 12
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ROM_SUPER_1:
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.word 0x93929190
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.word 0x97969594
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.word 0x9B9A9998
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.word 0x9F9E9D9C*/
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test51: //user read/write
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li TEST_ID, 51
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li x1, 0x90011008
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li x2, 0x5B5A5958
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lw x1, 0(x1)
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bne x1, x2, fail
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li x1, 0xA000A324
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li x2, 0xAAEE0008
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sw x2, 0(x1)
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lw x1, 0(x1)
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bne x1, x2, fail
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test52: //user fetch
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li TEST_ID, 52
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la x1, test53
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li x2, 0x90012010
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jr x2
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j fail
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test53: // user fetch page fault
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li TEST_ID, 53
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li TRAP_OK, 1
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la TRAP_RET, test54
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li x1, 0x90014390
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jr x1
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j fail
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test54: //user load page fault
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li TEST_ID, 54
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li TRAP_OK, 1
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la TRAP_RET, test55
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li x1, 0x90014394
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lw x1, 0(x1)
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j fail
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test55: //user store page fault
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li TEST_ID, 55
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li TRAP_OK, 1
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la TRAP_RET, test56
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li x1, 0x90014398
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sw x1, 0(x1)
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j fail
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test56:
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li TRAP_OK, 2
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ecall
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@ -407,7 +407,10 @@ public:
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uint32_t w : 1;
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uint32_t x : 1;
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uint32_t u : 1;
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uint32_t _dummy : 5;
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uint32_t g : 1;
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uint32_t a : 1;
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uint32_t d : 1;
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uint32_t _dummy : 2;
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uint32_t ppn : 22;
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};
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struct __attribute__((packed)){
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@ -505,9 +508,9 @@ public:
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}
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if(!tlb.u && effectivePrivilege == 0) return true;
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if( tlb.u && effectivePrivilege == 1 && !status.sum) return true;
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if(superPage && tlb.ppn0 != 0) return true;
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if(superPage && tlb.ppn0 != 0 || !tlb.a) return true;
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if(kind == READ || kind == READ_WRITE) if(!tlb.r && !(status.mxr && tlb.x)) return true;
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if(kind == WRITE || kind == READ_WRITE) if(!tlb.w) return true;
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if(kind == WRITE || kind == READ_WRITE) if(!tlb.w || !tlb.d) return true;
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if(kind == EXECUTE) if(!tlb.x) return true;
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*p = (tlb.ppn1 << 22) | (superPage ? v & 0x3FF000 : tlb.ppn0 << 12) | (v & 0xFFF);
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@ -628,6 +631,9 @@ public:
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default: return true; break;
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}
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// if(csr == MSTATUS || csr == SSTATUS){
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// printf("READ %x %x\n", pc, *value);
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// }
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return false;
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}
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@ -644,6 +650,9 @@ public:
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virtual bool csrWrite(int32_t csr, uint32_t value){
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if(((csr >> 8) & 0x3) > privilege) return true;
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// if(csr == MSTATUS || csr == SSTATUS){
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// printf("MIAOU %x %x\n", pc, value);
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// }
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switch(csr){
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case MSTATUS: status.raw = value & 0x7FFFFFFF; break;
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case MIP: ipSoft = value; break;
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@ -675,6 +684,9 @@ public:
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default: ilegalInstruction(); return true; break;
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}
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// if(csr == MSTATUS || csr == SSTATUS){
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// printf(" %x %x\n", pc, status.raw);
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// }
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return false;
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}
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@ -7,7 +7,7 @@ Disassembly of section .crt_section:
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80000000 <_start>:
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80000000: 00000e93 li t4,0
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80000004: 00000097 auipc ra,0x0
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80000008: 4ec08093 addi ra,ra,1260 # 800004f0 <trap>
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80000008: 4fc08093 addi ra,ra,1276 # 80000500 <trap>
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8000000c: 30509073 csrw mtvec,ra
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80000010 <test1>:
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@ -360,38 +360,38 @@ Disassembly of section .crt_section:
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800004c0 <fail>:
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800004c0: 00000e93 li t4,0
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800004c4: 00000073 ecall
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800004c4: 00000f17 auipc t5,0x0
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800004c8: 00cf0f13 addi t5,t5,12 # 800004d0 <failFence>
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800004cc: 00000073 ecall
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800004c8 <failFence>:
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800004c8: f0100137 lui sp,0xf0100
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800004cc: f2410113 addi sp,sp,-220 # f00fff24 <test56+0x700f2e68>
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800004d0: 01c12023 sw t3,0(sp)
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800004d0 <failFence>:
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800004d0: f0100137 lui sp,0xf0100
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800004d4: f2410113 addi sp,sp,-220 # f00fff24 <test56+0x700f2e68>
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800004d8: 01c12023 sw t3,0(sp)
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800004d4 <pass>:
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800004d4: 00200e93 li t4,2
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800004d8: 00000073 ecall
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800004dc <pass>:
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800004dc: 00100e93 li t4,1
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800004e0: 00000f17 auipc t5,0x0
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800004e4: 00cf0f13 addi t5,t5,12 # 800004ec <passFence>
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800004e8: 00000073 ecall
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800004dc <passFence>:
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800004dc: f0100137 lui sp,0xf0100
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800004e0: f2010113 addi sp,sp,-224 # f00fff20 <test56+0x700f2e64>
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800004e4: 00012023 sw zero,0(sp)
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800004e8: 00000013 nop
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800004ec: 00000013 nop
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800004ec <passFence>:
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800004ec: f0100137 lui sp,0xf0100
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800004f0: f2010113 addi sp,sp,-224 # f00fff20 <test56+0x700f2e64>
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800004f4: 00012023 sw zero,0(sp)
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800004f8: 00000013 nop
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800004fc: 00000013 nop
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800004f0 <trap>:
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800004f0: fc0e88e3 beqz t4,800004c0 <fail>
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800004f4: 342020f3 csrr ra,mcause
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800004f8: 341020f3 csrr ra,mepc
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800004fc: 300020f3 csrr ra,mstatus
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80000500: 343020f3 csrr ra,mtval
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80000504: 00200093 li ra,2
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80000508: fc1e86e3 beq t4,ra,800004d4 <pass>
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8000050c: 341f1073 csrw mepc,t5
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80000510: 30200073 mret
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80000514: 00000013 nop
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80000518: 00000013 nop
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8000051c: 00000013 nop
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80000520: 00000013 nop
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80000500 <trap>:
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80000500: fc0e80e3 beqz t4,800004c0 <fail>
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80000504: 342020f3 csrr ra,mcause
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80000508: 341020f3 csrr ra,mepc
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8000050c: 300020f3 csrr ra,mstatus
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80000510: 343020f3 csrr ra,mtval
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80000514: 00200093 li ra,2
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80000518: fc1e82e3 beq t4,ra,800004dc <pass>
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8000051c: 341f1073 csrw mepc,t5
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80000520: 30200073 mret
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80000524: 00000013 nop
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80000528: 00000013 nop
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8000052c: 00000013 nop
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