Hardware/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-01-03 03:43:39 -05:00
Code Issues Projects Releases Packages Wiki Activity

IBusSimplePlugin ensure AHB persistance

Browse source
This commit is contained in:
Dolu1990 2021-03-31 19:03:38 +02:00
parent 9ac6625ef3
commit a42c089119
1 changed files with 1 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View file

@ -180,6 +180,7 @@ case class IBusSimpleBus(plugin: IBusSimplePlugin) extends Bundle with IMasterSl
//cmdForkPersistence need to bet set
def toAhbLite3Master(): AhbLite3Master = {
assert(plugin.cmdForkPersistence)
val bus = AhbLite3Master(IBusSimpleBus.getAhbLite3Config())
bus.HADDR := this.cmd.pc
bus.HWRITE := False