Fix typo

2017-07-16 20:41:03 +02:00 · 2017-07-16 20:41:03 +02:00 · a4ac2ca8ce
parent 5190ba28e0
commit a4ac2ca8ce
1 changed files with 1 additions and 1 deletions
--- a/README.md
+++ b/README.md
@ -17,7 +17,7 @@ This repository host an RISC-V implementation written in SpinalHDL. There is som

 - RV32IM instruction set
 - Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
- 1.16 DMIPS/Mhz when all features are enabled extension
+- 1.16 DMIPS/Mhz when all features are enabled
 - Optimized for FPGA
 - Optional MUL/DIV extension
 - Optional instruction and data caches