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VexRiscv
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Fix typo

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Dolu1990 2017-07-16 20:41:03 +02:00
parent 5190ba28e0
commit a4ac2ca8ce
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@ -17,7 +17,7 @@ This repository host an RISC-V implementation written in SpinalHDL. There is som
- RV32IM instruction set - RV32IM instruction set
- Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack) - Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
- 1.16 DMIPS/Mhz when all features are enabled extension - 1.16 DMIPS/Mhz when all features are enabled
- Optimized for FPGA - Optimized for FPGA
- Optional MUL/DIV extension - Optional MUL/DIV extension
- Optional instruction and data caches - Optional instruction and data caches