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VexRiscv
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Typo fix

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Charles Papon 2017-08-01 00:01:52 +02:00
parent e3411012d7
commit a4d99d734b
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README.md
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@ -214,7 +214,7 @@ To connect OpenOCD (https://github.com/SpinalHDL/openocd_riscv) to the simulatio
```sh ```sh
src/openocd -f tcl/interface/jtag_tcp.cfg -c "set BRIEY_CPU0_YAML /home/spinalvm/Spinal/VexRiscv/cpu0.yaml" -f tcl/target/briey.cfg src/openocd -f tcl/interface/jtag_tcp.cfg -c "set BRIEY_CPU0_YAML /home/spinalvm/Spinal/VexRiscv/cpu0.yaml" -f tcl/target/briey.cfg
```§ ```
You can find multiples software examples and demo there : https://github.com/SpinalHDL/VexRiscvSocSoftware/tree/master/projects/briey You can find multiples software examples and demo there : https://github.com/SpinalHDL/VexRiscvSocSoftware/tree/master/projects/briey