Fix IBusCachedPlugin Pass all dhrystone tests
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@ -48,7 +48,7 @@ object TestsWorkspace {
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cpuDataWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = false,
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catchIllegalAccess = false,
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catchAccessFault = false,
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catchAccessFault = true,
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catchMemoryTranslationMiss = false,
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catchMemoryTranslationMiss = false,
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asyncTagMemory = false,
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asyncTagMemory = false,
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twoCycleRam = false
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twoCycleRam = false
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@ -379,7 +379,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
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when(enable){
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when(enable){
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fetcher.haltIt()
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fetcher.haltIt()
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}
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}
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val done = ! List(execute, memory, writeBack).map(_.arbitration.isValid).orR && fetcher.nextPc()._1
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val done = ! List(execute, memory, writeBack).map(_.arbitration.isValid).orR && !fetcher.nextPc()._1
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// val done = History(doneAsync, 0 to 0).andR
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// val done = History(doneAsync, 0 to 0).andR
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}
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}
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@ -27,9 +27,9 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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assert(cmdToRspStageCount >= 1)
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assert(cmdToRspStageCount >= 1)
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assert(!(compressedGen && !decodePcGen))
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assert(!(compressedGen && !decodePcGen))
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var fetcherHalt : Bool = null
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var fetcherHalt : Bool = null
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lazy val decodeNextPcValid = Bool
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lazy val decodeNextPcValid = Bool //TODO remove me ?
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lazy val decodeNextPc = UInt(32 bits)
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lazy val decodeNextPc = UInt(32 bits)
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def nextPc() = (decodeNextPcValid, decodeNextPc)
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def nextPc() = (False, decodeNextPc)
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var predictionJumpInterface : Flow[UInt] = null
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var predictionJumpInterface : Flow[UInt] = null
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@ -230,7 +230,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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bufferValid clearWhen(output.fire)
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bufferValid clearWhen(output.fire)
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when(input.ready){
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when(input.ready){
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when(input.valid) {
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when(input.valid) {
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bufferValid := !(!isRvc && !input.pc(1) && !bufferValid) && !(isRvc && input.pc(1))
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bufferValid := !(!isRvc && !input.pc(1) && !bufferValid) && !(isRvc && input.pc(1) && output.ready)
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bufferData := input.rsp.inst(31 downto 16)
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bufferData := input.rsp.inst(31 downto 16)
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}
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}
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}
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}
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@ -238,18 +238,19 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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iBusRsp.readyForError.clearWhen(bufferValid && isRvc)
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iBusRsp.readyForError.clearWhen(bufferValid && isRvc)
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})
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})
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//TODO never colalpse buble of the last stage
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def condApply[T](that : T, cond : Boolean)(func : (T) => T) = if(cond)func(that) else that
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def condApply[T](that : T, cond : Boolean)(func : (T) => T) = if(cond)func(that) else that
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val injector = new Area {
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val injector = new Area {
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val inputBeforeHalt = condApply(if(decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(flush))
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val inputBeforeHalt = condApply(if(decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(flush))
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if(injectorReadyCutGen) iBusRsp.readyForError.clearWhen(inputBeforeHalt.valid)
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if(injectorReadyCutGen) iBusRsp.readyForError.clearWhen(inputBeforeHalt.valid)
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val decodeInput = if(injectorStage){
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val decodeInput = (if(injectorStage){
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val decodeInput = inputBeforeHalt.m2sPipeWithFlush(killLastStage)
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val decodeInput = inputBeforeHalt.m2sPipeWithFlush(killLastStage, collapsBubble = false)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeHalt.rsp.inst)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeHalt.rsp.inst)
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iBusRsp.readyForError.clearWhen(decodeInput.valid)
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iBusRsp.readyForError.clearWhen(decodeInput.valid)
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decodeInput
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decodeInput
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} else {
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} else {
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inputBeforeHalt
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inputBeforeHalt
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}.haltWhen(fetcherHalt)
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}).haltWhen(fetcherHalt)
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if(decodePcGen){
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if(decodePcGen){
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decodeNextPcValid := True
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decodeNextPcValid := True
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@ -28,6 +28,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConf
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var mmuBus : MemoryTranslatorBus = null
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var mmuBus : MemoryTranslatorBus = null
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var privilegeService : PrivilegeService = null
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var privilegeService : PrivilegeService = null
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var redoBranch : Flow[UInt] = null
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var redoBranch : Flow[UInt] = null
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var decodeExceptionPort : Flow[ExceptionCause] = null
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object FLUSH_ALL extends Stageable(Bool)
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object FLUSH_ALL extends Stageable(Bool)
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object IBUS_ACCESS_ERROR extends Stageable(Bool)
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object IBUS_ACCESS_ERROR extends Stageable(Bool)
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@ -50,10 +51,10 @@ class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConf
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redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(pipeline.decode, priority = 1) //Priority 1 will win against branch predictor
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redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(pipeline.decode, priority = 1) //Priority 1 will win against branch predictor
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// if(catchSomething) {
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if(catchSomething) {
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// val exceptionService = pipeline.service(classOf[ExceptionService])
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val exceptionService = pipeline.service(classOf[ExceptionService])
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// decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1)
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decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1)
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// }
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}
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// if(pipeline.serviceExist(classOf[MemoryTranslator]))
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// if(pipeline.serviceExist(classOf[MemoryTranslator]))
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// ??? //TODO
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// ??? //TODO
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@ -82,6 +83,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConf
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}
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}
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}
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}
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override def build(pipeline: VexRiscv): Unit = {
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline._
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import pipeline.config._
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import pipeline.config._
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@ -99,7 +101,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConf
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//Connect fetch cache side
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//Connect fetch cache side
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cache.io.cpu.fetch.isValid := iBusRsp.inputPipeline(0).valid
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cache.io.cpu.fetch.isValid := iBusRsp.inputPipeline(0).valid
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cache.io.cpu.fetch.isStuck := !iBusRsp.inputPipeline(0).ready
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cache.io.cpu.fetch.isStuck := !iBusRsp.input.ready
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cache.io.cpu.fetch.pc := iBusRsp.inputPipeline(0).payload
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cache.io.cpu.fetch.pc := iBusRsp.inputPipeline(0).payload
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if (mmuBus != null) {
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if (mmuBus != null) {
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@ -114,15 +116,43 @@ class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConf
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cache.io.cpu.fetch.mmuBus.rsp.miss := False
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cache.io.cpu.fetch.mmuBus.rsp.miss := False
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}
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}
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val missHalt = cache.io.cpu.fetch.isValid && cache.io.cpu.fetch.cacheMiss
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// val missHalt = cache.io.cpu.fetch.isValid && cache.io.cpu.fetch.cacheMiss
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iBusRsp.outputBeforeStage.arbitrationFrom(iBusRsp.inputPipeline(0).haltWhen(missHalt))
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var issueDetected = False
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val redoFetch = False //RegNext(False) init(False)
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when(cache.io.cpu.fetch.isValid && cache.io.cpu.fetch.cacheMiss && !issueDetected){
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issueDetected \= True
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redoFetch := iBusRsp.readyForError
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// if(decodePcGen) {
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// redoFetch := !flush && iBusRsp.readyForError
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// } else {
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// redoFetch := !flush && iBusRsp.readyForError
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// }
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}
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cache.io.cpu.fill.valid := redoFetch
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redoBranch.valid := redoFetch
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assert(decodePcGen == compressedGen)
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redoBranch.payload := (if(decodePcGen) decode.input(PC) else cache.io.cpu.fetch.pc)
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cache.io.cpu.fill.payload := cache.io.cpu.fetch.pc
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if(catchSomething){
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// val missHalt = cache.io.cpu.fetch.isValid && cache.io.cpu.fetch.cacheMiss
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decodeExceptionPort.valid := False
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decodeExceptionPort.code := 1
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decodeExceptionPort.badAddr := cache.io.cpu.fetch.pc
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when(cache.io.cpu.fetch.isValid && cache.io.cpu.fetch.error && !issueDetected){
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issueDetected \= True
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decodeExceptionPort.valid := iBusRsp.readyForError
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}
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}
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iBusRsp.outputBeforeStage.arbitrationFrom(iBusRsp.inputPipeline(0).haltWhen(issueDetected))
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iBusRsp.outputBeforeStage.rsp.inst := cache.io.cpu.fetch.data
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iBusRsp.outputBeforeStage.rsp.inst := cache.io.cpu.fetch.data
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iBusRsp.outputBeforeStage.pc := iBusRsp.inputPipeline(0).payload
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iBusRsp.outputBeforeStage.pc := iBusRsp.inputPipeline(0).payload
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cache.io.cpu.fill.valid := missHalt && iBusRsp.readyForError
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cache.io.cpu.fill.payload := cache.io.cpu.fetch.pc
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redoBranch.valid := (RegNext(cache.io.cpu.fill.valid && !flush) init(False))
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redoBranch.payload := decode.input(PC)
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// if (dataOnDecode) {
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// if (dataOnDecode) {
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// decode.insert(INSTRUCTION) := cache.io.cpu.decode.data
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// decode.insert(INSTRUCTION) := cache.io.cpu.decode.data
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// } else {
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// } else {
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@ -1 +1 @@
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.word 0x301c63
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.word 0xc12083
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