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VexRiscv
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Add opcode for clean/invalidate the datacache 

Change mmu opcodes
This commit is contained in:
Charles Papon 2017-05-07 16:02:55 +02:00
parent 4d6a6fbb02
commit a51c27970b
4 changed files with 24 additions and 19 deletions
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20
src/main/scala/SpinalRiscv/Plugin/DBusCachedPlugin.scala
View File

@ -65,6 +65,12 @@ class DBusCachedPlugin(config : DataCacheConfig, askMemoryTranslation : Boolean
List(SB, SH, SW).map(_ -> storeActions)
)
def MANAGEMENT = M"-------00000-----101-----0001111"
decoderService.add(MANAGEMENT, stdActions ++ List(
SRC2_CTRL -> Src2CtrlEnum.RS,
REG2_USE -> True
))
if(askMemoryTranslation)
mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(pipeline.memory,memoryTranslatorPortConfig)
@ -97,11 +103,11 @@ class DBusCachedPlugin(config : DataCacheConfig, askMemoryTranslation : Boolean
default -> input(REG2)(31 downto 0)
)
cache.io.cpu.execute.args.size := size
cache.io.cpu.execute.args.forceUncachedAccess := False // cache.io.cpu.execute.args.address(31 downto 28) === 0xF
cache.io.cpu.execute.args.kind := DataCacheCpuCmdKind.MEMORY
cache.io.cpu.execute.args.clean := False
cache.io.cpu.execute.args.invalidate := False
cache.io.cpu.execute.args.way := False
cache.io.cpu.execute.args.forceUncachedAccess := False
cache.io.cpu.execute.args.kind := input(INSTRUCTION)(2) ? DataCacheCpuCmdKind.MANAGMENT | DataCacheCpuCmdKind.MEMORY
cache.io.cpu.execute.args.clean := input(INSTRUCTION)(28)
cache.io.cpu.execute.args.invalidate := input(INSTRUCTION)(29)
cache.io.cpu.execute.args.way := input(INSTRUCTION)(30)
insert(MEMORY_ADDRESS_LOW) := cache.io.cpu.execute.args.address(1 downto 0)
}
@ -234,7 +240,7 @@ object Bypasser{
}
object DataCacheCpuCmdKind extends SpinalEnum{
val MEMORY,LINE = newElement()
val MEMORY,MANAGMENT = newElement()
}
object DataCacheCpuExecute{
@ -605,7 +611,7 @@ class DataCache(p : DataCacheConfig) extends Component{
io.cpu.writeBack.mmuMiss := mmuRsp.miss
}
switch(request.kind) {
is(LINE) {
is(MANAGMENT) {
when(delayedIsStuck && !mmuRsp.miss) {
when(delayedWaysHitValid || (request.way && way.tagReadRspTwo.used)) {
io.cpu.writeBack.haltIt.clearWhen(!(victim.requestIn.valid && !victim.requestIn.ready))

1
src/main/scala/SpinalRiscv/Plugin/MachineCsr.scala
View File

@ -304,7 +304,6 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
)
mcause.interrupt := interrupt
mcause.exceptionCode := ((mip.MEIP && mie.MEIE) ? U(11) | ((mip.MSIP && mie.MSIE) ? U(3) | U(7)))
}

6
src/main/scala/SpinalRiscv/Plugin/MemoryTranslatorPlugin.scala
View File

@ -27,8 +27,8 @@ class MemoryTranslatorPlugin(tlbSize : Int,
override def setup(pipeline: VexRiscv): Unit = {
import Riscv._
import pipeline.config._
def TLBW0 = M"0000000----------000-----0101011"
def TLBW1 = M"0000000----------001-----0101011"
def TLBW0 = M"0000000----------111-----0001111"
def TLBW1 = M"0000001----------111-----0001111"
val decoderService = pipeline.service(classOf[DecoderService])
decoderService.addDefault(IS_TLB, False)
decoderService.add(TLBW0, List(IS_TLB -> True, REG1_USE -> True, SRC1_CTRL -> Src1CtrlEnum.RS))
@ -124,7 +124,7 @@ class MemoryTranslatorPlugin(tlbSize : Int,
import execute._
val tlbWriteBuffer = Reg(UInt(20 bits))
when(arbitration.isFiring && input(IS_TLB)){
switch(input(INSTRUCTION)(funct3Range)){
switch(input(INSTRUCTION)(25 downto 25)){
is(0){
tlbWriteBuffer := input(SRC1).asUInt.resized
}

16
src/test/resources/hex/mmu.hex
View File

@ -1,14 +1,14 @@
:100000006F00000413000000130000001300000044
:100010001300000013000000130000001300000094
:10002000732E2034732E3034B74E0C00370F01F08E
:10003000930F40002B800E002B90EF0173002030B7
:10004000130E10001303F0011303F3FF2B10030032
:10003000930F40000FF00E000FF0EF03730020301D
:10004000130E10001303F0011303F3FF0F700302EC
:10005000E31C03FE130E200037020C00B70201F070
:10006000130300002B0002002B10530037120C006A
:10007000B70201F0130310002B0002002B105300F5
:1000800037220C00B70202F0130320002B000200FD
:100090002B10530037320C00B70202F0130330006C
:1000A0002B0002002B105300130E300037020010FB
:10006000130300000F7002000F70530237120C00D0
:10007000B70201F0130310000F7002000F7053025B
:1000800037220C00B70202F0130320000F700200A9
:100090000F70530237320C00B70202F01303300026
:1000A0000F7002000F705302130E30003702001061
:1000B000B70200C0370300C1B7030020370400C2F5
:1000C000B70400C3370500C4371611111306161103
:1000D000B726222293862622373733331307373346
@ -17,7 +17,7 @@
:10010000130E4000032E02002320E30003AE020082
:10011000032E0200130E5000032E0500130E600084
:10012000130E700037620C00B70200F01303F001E9
:100130002B0002002B1053001300000013000000DE
:100130000F7002000F705302130000001300000044
:10014000130000001300000013000000370200C677
:1001500067000200130000001300000013000000FD
:08016000130000001300000071