Add flush support instruction into the instruction cache

This commit is contained in:
Charles Papon 2017-05-19 11:20:33 +02:00
parent 736478ff1d
commit a5364ad001
4 changed files with 30 additions and 7 deletions

View File

@ -382,10 +382,11 @@ class CsrPlugin(config : MachineCsrConfig) extends Plugin[VexRiscv] with Excepti
val imm = IMM(input(INSTRUCTION))
val writeSrc = input(INSTRUCTION)(14) ? imm.z.asBits.resized | input(SRC1)
val readData = B(0, 32 bits)
def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT
val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid && !memory.arbitration.isStuck) clearWhen(!arbitration.isStuck)
val writeData = input(INSTRUCTION)(13).mux(
False -> writeSrc,
True -> Mux(input(INSTRUCTION)(12), memory.input(REGFILE_WRITE_DATA) & ~writeSrc, memory.input(REGFILE_WRITE_DATA) | writeSrc)
True -> Mux(input(INSTRUCTION)(12), readDataReg & ~writeSrc, readDataReg | writeSrc)
)
val writeOpcode = (!((input(INSTRUCTION)(14 downto 13) === "01" && input(INSTRUCTION)(rs1Range) === 0)
|| (input(INSTRUCTION)(14 downto 13) === "11" && imm.z === 0)))

View File

@ -15,10 +15,19 @@ class IBusCachedPlugin(config : InstructionCacheConfig, askMemoryTranslation : B
var decodeExceptionPort : Flow[ExceptionCause] = null
var privilegeService : PrivilegeService = null
object FLUSH_ALL extends Stageable(Bool)
object IBUS_ACCESS_ERROR extends Stageable(Bool)
override def setup(pipeline: VexRiscv): Unit = {
pipeline.unremovableStages += pipeline.prefetch
import Riscv._
import pipeline.config._
def MANAGEMENT = M"-----------------100-----0001111"
val decoderService = pipeline.service(classOf[DecoderService])
decoderService.addDefault(FLUSH_ALL, False)
decoderService.add(MANAGEMENT, List(
FLUSH_ALL -> True
))
if(catchSomething) {
val exceptionService = pipeline.service(classOf[ExceptionService])
@ -68,7 +77,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig, askMemoryTranslation : B
}
}
cache.io.flush.cmd.valid := False
if(twoStageLogic){
cache.io.cpu.decode.isValid := decode.arbitration.isValid
@ -96,5 +105,20 @@ class IBusCachedPlugin(config : InstructionCacheConfig, askMemoryTranslation : B
decodeExceptionPort.code := mmuMiss ? U(14) | 1
decodeExceptionPort.badAddr := decode.input(PC)
}
memory plug new Area{
import memory._
cache.io.flush.cmd.valid := False
when(arbitration.isValid && input(FLUSH_ALL)){
cache.io.flush.cmd.valid := True
when(!cache.io.flush.cmd.ready){
arbitration.haltIt := True
} otherwise {
decode.arbitration.flushAll := True
}
}
}
}
}

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@ -36,8 +36,6 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean)
object IBUS_ACCESS_ERROR extends Stageable(Bool)
var decodeExceptionPort : Flow[ExceptionCause] = null
override def setup(pipeline: VexRiscv): Unit = {
pipeline.unremovableStages += pipeline.prefetch
if(catchAccessFault) {
val exceptionService = pipeline.service(classOf[ExceptionService])
decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1)

View File

@ -393,6 +393,6 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
lineLoader.requestIn.addr := mmuRsp.physicalAddress
}
io.flush.cmd.ready := !(lineLoader.request.valid || io.cpu.fetch.isValid)
io.flush.cmd.ready := !(lineLoader.request.valid || io.cpu.fetch.isValid || (if(twoStageLogic) io.cpu.decode.isValid else False))
}