Add an "allow" property to individual CSRs
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@ -344,13 +344,13 @@ case class CsrDuringWrite(doThat :() => Unit)
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case class CsrDuringRead(doThat :() => Unit)
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case class CsrDuring(doThat :() => Unit)
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case class CsrOnRead(doThat : () => Unit)
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case class CsrAllow()
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case class CsrMapping() extends CsrInterface{
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val mapping = mutable.LinkedHashMap[Int,ArrayBuffer[Any]]()
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val always = ArrayBuffer[Any]()
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val readDataSignal, readDataInit, writeDataSignal = Bits(32 bits)
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val allowCsrSignal = False
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val hazardFree = Bool()
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readDataSignal := readDataInit
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@ -368,7 +368,7 @@ case class CsrMapping() extends CsrInterface{
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override def duringAnyRead(body: => Unit) : Unit = always += CsrDuringWrite(() => body)
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override def readData() = readDataSignal
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override def writeData() = writeDataSignal
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override def allowCsr() = allowCsrSignal := True
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override def allow(csrAddress: Int): Unit = addMappingAt(csrAddress, CsrAllow())
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override def isHazardFree() = hazardFree
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}
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@ -386,9 +386,9 @@ trait CsrInterface{
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r(csrAddress,bitOffset,that)
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w(csrAddress,bitOffset,that)
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}
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def allow(csrAddress: Int): Unit
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def duringAnyWrite(body: => Unit) : Unit //Called all the durration of a Csr write instruction in the execute stage
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def duringAnyRead(body: => Unit) : Unit //same than above for read
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def allowCsr() : Unit //In case your csr do not use the regular API with csrAddress but is implemented using "side channels", you can call that if the current csr is implemented
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def isHazardFree() : Bool // You should not have any side effect nor use readData() until this return True
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def r2w(csrAddress : Int, bitOffset : Int,that : Data): Unit
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@ -517,7 +517,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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override def duringAny(): Bool = pipeline.execute.arbitration.isValid && pipeline.execute.input(IS_CSR)
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override def duringAnyWrite(body: => Unit) = csrMapping.duringAnyWrite(body)
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override def duringAnyRead(body: => Unit) = csrMapping.duringAnyRead(body)
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override def allowCsr() = csrMapping.allowCsr()
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override def allow(csrAddress: Int): Unit = csrMapping.allow(csrAddress)
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override def readData() = csrMapping.readData()
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override def writeData() = csrMapping.writeData()
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override def isHazardFree() = csrMapping.isHazardFree()
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@ -1181,6 +1181,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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} else {
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if (withWrite) illegalAccess.clearWhen(input(CSR_WRITE_OPCODE))
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if (withRead) illegalAccess.clearWhen(input(CSR_READ_OPCODE))
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if (jobs.exists(j => j.isInstanceOf[CsrAllow])) illegalAccess := False
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}
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@ -1266,8 +1267,6 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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case element : CsrDuringRead => when(readInstruction){element.doThat()}
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}
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illegalAccess clearWhen(csrMapping.allowCsrSignal)
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when(privilege < csrAddress(9 downto 8).asUInt){
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illegalAccess := True
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readInstruction := False
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@ -178,13 +178,16 @@ class PmpPlugin(regions : Int, granularity : Int, ioRange : UInt => Bool) extend
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val writeData = csrService.writeData()
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val enable = RegInit(False)
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for (i <- 0 until regions) {
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csrService.onRead(0x3b0 + i) {csrService.readData().assignFromBits(cfgRegister(pmpSelect)) }
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csrService.onWrite(0x3b0 + i) { enable := True }
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for (i <- 0 until regions) csrService.allow(0x3b0 + i)
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for (i <- 0 until (regions / 4)) csrService.allow(0x3a0 + i)
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csrService.duringAnyRead {
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when (input(PMPCFG)) { csrService.readData().assignFromBits(cfgRegister(pmpSelect)) }
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when (input(PMPADDR)) { csrService.readData() := pmpaddr.readAsync(pmpIndex).asBits }
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}
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for (i <- 0 until (regions / 4)) {
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csrService.onRead(0x3a0 + i) { csrService.readData() := pmpaddr.readAsync(pmpIndex).asBits }
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csrService.onWrite(0x3a0 + i) { enable := True }
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csrService.duringAnyWrite {
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when (input(PMPCFG) | input(PMPADDR)) { enable := True }
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}
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val writer = new Area {
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