Add CsrPlugin external hartid
d$ rsp/sync now decrement pendings by signal amount
This commit is contained in:
Dolu1990
parent
380afa3130
commit
a64fd9cf3b
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@ -54,8 +54,9 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
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val core = new VexRiscv(cpuConfig)
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core.plugins.foreach {
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case plugin: IBusCachedPlugin => iBus = plugin.iBus.toBmb()
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case plugin: DBusCachedPlugin => dBus = plugin.dBus.toBmb()
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case plugin: DBusCachedPlugin => dBus = plugin.dBus.toBmb().pipelined(cmdValid = true)
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case plugin: CsrPlugin => {
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plugin.externalMhartId := cpuId
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plugin.softwareInterrupt := io.softwareInterrupts(cpuId)
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plugin.externalInterrupt := io.externalInterrupts(cpuId)
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plugin.timerInterrupt := io.timerInterrupts(cpuId)
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@ -112,9 +113,12 @@ case class VexRiscvSmpCluster(p : VexRiscvSmpClusterParameter,
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object VexRiscvSmpClusterGen {
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def vexRiscvConfig(hartId : Int,
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def vexRiscvConfig(hartIdWidth : Int,
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hartId : Int,
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ioRange : UInt => Bool = (x => x(31 downto 28) === 0xF),
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resetVector : Long = 0x80000000l) = {
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val iBusWidth = 128
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val dBusWidth = 64
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val config = VexRiscvConfig(
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plugins = List(
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new MmuPlugin(
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@ -135,7 +139,7 @@ object VexRiscvSmpClusterGen {
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wayCount = 2,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 128,
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memDataWidth = iBusWidth,
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catchIllegalAccess = true,
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catchAccessFault = true,
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asyncTagMemory = false,
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@ -151,7 +155,7 @@ object VexRiscvSmpClusterGen {
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)
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),
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new DBusCachedPlugin(
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dBusCmdMasterPipe = true,
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dBusCmdMasterPipe = dBusWidth == 32,
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dBusCmdSlavePipe = true,
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dBusRspSlavePipe = true,
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relaxedMemoryTranslationRegister = true,
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@ -161,14 +165,15 @@ object VexRiscvSmpClusterGen {
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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memDataWidth = dBusWidth,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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withLrSc = true,
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withAmo = true,
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withExclusive = true,
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withInvalidate = true
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withInvalidate = true,
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aggregationWidth = if(dBusWidth == 32) 0 else log2Up(dBusWidth/8)
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// )
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),
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memoryTranslatorPortConfig = MmuPortConfig(
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@ -208,7 +213,7 @@ object VexRiscvSmpClusterGen {
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mulUnrollFactor = 32,
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divUnrollFactor = 1
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),
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new CsrPlugin(CsrPluginConfig.openSbi(hartId = hartId, misa = Riscv.misaToInt("imas"))),
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new CsrPlugin(CsrPluginConfig.openSbi(misa = Riscv.misaToInt("imas")).copy(withExternalMhartid = true, mhartidWidth = hartIdWidth)),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true,
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@ -224,7 +229,7 @@ object VexRiscvSmpClusterGen {
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debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn")),
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p = VexRiscvSmpClusterParameter(
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cpuConfigs = List.tabulate(cpuCount) {
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vexRiscvConfig(_, resetVector = resetVector)
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vexRiscvConfig(log2Up(cpuCount), _, resetVector = resetVector)
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}
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)
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)
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@ -462,7 +467,7 @@ object VexRiscvSmpClusterOpenSbi extends App{
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simConfig.allOptimisation
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simConfig.addSimulatorFlag("--threads 1")
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val cpuCount = 1
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val cpuCount = 4
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val withStall = false
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def gen = {
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@ -573,8 +578,8 @@ object VexRiscvSmpClusterOpenSbi extends App{
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// fork{
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// disableSimWave()
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// val atMs = 130
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// val durationMs = 15
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// val atMs = 3790
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// val durationMs = 5
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// sleep(atMs*1000000)
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// enableSimWave()
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// println("** enableSimWave **")
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@ -73,13 +73,13 @@ case class LiteDramNative(p : LiteDramNativeParameter) extends Bundle with IMast
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}
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var writeCmdCounter, writeDataCounter = 0
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StreamReadyRandomizer(bus.cmd, cd)
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StreamReadyRandomizer(bus.cmd, cd).factor = 0.5f
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StreamMonitor(bus.cmd, cd) { t =>
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cmdQueue.enqueue(Cmd(t.addr.toLong * (p.dataWidth/8) , t.we.toBoolean))
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if(t.we.toBoolean) writeCmdCounter += 1
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}
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StreamReadyRandomizer(bus.wdata, cd)
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StreamReadyRandomizer(bus.wdata, cd).factor = 0.5f
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StreamMonitor(bus.wdata, cd) { p =>
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writeDataCounter += 1
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// if(p.data.toBigInt == BigInt("00000002000000020000000200000002",16)){
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@ -175,16 +175,19 @@ case class BmbToLiteDram(bmbParameter : BmbParameter,
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val halt = Bool()
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val (cmdFork, dataFork) = StreamFork2(unburstified.cmd.haltWhen(halt))
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io.output.cmd.arbitrationFrom(cmdFork.haltWhen(pendingRead.msb))
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io.output.cmd.addr := (cmdFork.address >> log2Up(liteDramParameter.dataWidth/8)).resized
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io.output.cmd.we := cmdFork.isWrite
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val outputCmd = Stream(LiteDramNativeCmd(liteDramParameter))
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outputCmd.arbitrationFrom(cmdFork.haltWhen(pendingRead.msb))
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outputCmd.addr := (cmdFork.address >> log2Up(liteDramParameter.dataWidth/8)).resized
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outputCmd.we := cmdFork.isWrite
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io.output.cmd <-< outputCmd
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if(bmbParameter.canWrite) {
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val wData = Stream(LiteDramNativeWData(liteDramParameter))
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wData.arbitrationFrom(dataFork.throwWhen(dataFork.isRead))
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wData.data := dataFork.data
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wData.we := dataFork.mask
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io.output.wdata << wData.queue(wdataFifoSize)
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io.output.wdata << wData.queueLowLatency(wdataFifoSize, latency = 1) //TODO queue low latency
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} else {
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dataFork.ready := True
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io.output.wdata.valid := False
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@ -212,7 +215,7 @@ case class BmbToLiteDram(bmbParameter : BmbParameter,
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unburstified.rsp.data := rdataFifo.data
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pendingRead := pendingRead + U(io.output.cmd.fire && !io.output.cmd.we) - U(rdataFifo.fire)
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pendingRead := pendingRead + U(outputCmd.fire && !outputCmd.we) - U(rdataFifo.fire)
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}
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object BmbToLiteDramTester extends App{
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@ -241,6 +244,7 @@ case class VexRiscvLitexSmpClusterParameter( cluster : VexRiscvSmpClusterParamet
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liteDram : LiteDramNativeParameter,
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liteDramMapping : AddressMapping)
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//addAttribute("""mark_debug = "true"""")
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case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
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debugClockDomain : ClockDomain) extends Component{
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@ -308,50 +312,59 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
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iBusDecoder.io.input << iBusArbiter.io.output.pipelined(cmdValid = true)
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val iMem = LiteDramNative(p.liteDram)
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val iMemBridge = iMem.fromBmb(iBusDecoder.io.outputs(1), wdataFifoSize = 0, rdataFifoSize = 32)
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iMem.cmd >-> io.iMem.cmd
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iMem.wdata >> io.iMem.wdata
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iMem.rdata << io.iMem.rdata
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io.iMem.fromBmb(iBusDecoder.io.outputs(1), wdataFifoSize = 0, rdataFifoSize = 32)
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val iBusDecoderToPeripheral = iBusDecoder.io.outputs(0).resize(dataWidth = 32).pipelined(cmdHalfRate = true, rspValid = true)
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val dBusDecoderToPeripheral = dBusDecoder.io.outputs(0).resize(dataWidth = 32).pipelined(cmdHalfRate = true, rspValid = true)
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val peripheralAccessLength = Math.max(iBusDecoder.io.outputs(0).p.lengthWidth, dBusDecoder.io.outputs(0).p.lengthWidth)
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val peripheralArbiter = BmbArbiter(
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p = dBusDecoder.io.outputs(0).p.copy(sourceWidth = dBusDecoder.io.outputs(0).p.sourceWidth + 1, lengthWidth = peripheralAccessLength),
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p = dBusDecoder.io.outputs(0).p.copy(
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sourceWidth = List(iBusDecoderToPeripheral, dBusDecoderToPeripheral).map(_.p.sourceWidth).max + 1,
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contextWidth = List(iBusDecoderToPeripheral, dBusDecoderToPeripheral).map(_.p.contextWidth).max,
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lengthWidth = peripheralAccessLength,
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dataWidth = 32
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),
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portCount = 2,
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lowerFirstPriority = true
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)
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peripheralArbiter.io.inputs(0) << iBusDecoder.io.outputs(0).resize(dataWidth = 32).pipelined(cmdHalfRate = true, rspValid = true)
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peripheralArbiter.io.inputs(1) << dBusDecoder.io.outputs(0).resize(dataWidth = 32).pipelined(cmdHalfRate = true, rspValid = true)
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peripheralArbiter.io.inputs(0) << iBusDecoderToPeripheral
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peripheralArbiter.io.inputs(1) << dBusDecoderToPeripheral
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val peripheralWishbone = peripheralArbiter.io.output.pipelined(cmdValid = true).toWishbone()
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io.peripheral << peripheralWishbone
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}
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object VexRiscvLitexSmpClusterGen extends App {
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val cpuCount = 4
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for(cpuCount <- List(1,2,4,8)) {
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def parameter = VexRiscvLitexSmpClusterParameter(
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cluster = VexRiscvSmpClusterParameter(
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cpuConfigs = List.tabulate(cpuCount) { hartId =>
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vexRiscvConfig(
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hartIdWidth = log2Up(cpuCount),
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hartId = hartId,
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ioRange = address => address.msb,
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resetVector = 0
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)
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}
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),
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liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
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liteDramMapping = SizeMapping(0x40000000l, 0x40000000l)
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)
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def parameter = VexRiscvLitexSmpClusterParameter(
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cluster = VexRiscvSmpClusterParameter(
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cpuConfigs = List.tabulate(cpuCount) { hartId =>
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vexRiscvConfig(
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hartId = hartId,
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ioRange = address => address.msb,
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resetVector = 0
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)
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}
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),
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liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
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liteDramMapping = SizeMapping(0x40000000l, 0x40000000l)
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)
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def dutGen = {
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val toplevel = VexRiscvLitexSmpCluster(
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p = parameter,
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debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
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)
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toplevel
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}
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def dutGen = VexRiscvLitexSmpCluster(
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p = parameter,
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debugClockDomain = ClockDomain.current.copy(reset = Bool().setName("debugResetIn"))
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)
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val genConfig = SpinalConfig().addStandardMemBlackboxing(blackboxByteEnables)
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// genConfig.generateVerilog(Bench.compressIo(dutGen))
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genConfig.generateVerilog(dutGen)
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val genConfig = SpinalConfig().addStandardMemBlackboxing(blackboxByteEnables)
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// genConfig.generateVerilog(Bench.compressIo(dutGen))
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genConfig.generateVerilog(dutGen.setDefinitionName(s"VexRiscvLitexSmpCluster_${cpuCount}c"))
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}
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}
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@ -363,13 +376,13 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
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simConfig.withWave
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simConfig.allOptimisation
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val cpuCount = 4
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val withStall = false
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val cpuCount = 8
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def parameter = VexRiscvLitexSmpClusterParameter(
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cluster = VexRiscvSmpClusterParameter(
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cpuConfigs = List.tabulate(cpuCount) { hartId =>
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vexRiscvConfig(
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hartIdWidth = log2Up(cpuCount),
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hartId = hartId,
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ioRange = address => address(31 downto 28) === 0xF,
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resetVector = 0x80000000l
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@ -440,12 +453,12 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
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// fork{
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// disableSimWave()
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// val atMs = 8
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// val durationMs = 3
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// sleep(atMs*1000000)
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// val atMs = 3790
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// val durationMs = 5
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// sleep(atMs*1000000l)
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// enableSimWave()
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// println("** enableSimWave **")
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// sleep(durationMs*1000000)
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// sleep(durationMs*1000000l)
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// println("** disableSimWave **")
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// while(true) {
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// disableSimWave()
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@ -453,7 +466,7 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
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// enableSimWave()
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// sleep( 100 * 10)
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// }
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// // simSuccess()
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// // simSuccess()
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// }
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fork{
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@ -5,7 +5,7 @@ import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4Shared}
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import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
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import spinal.lib.bus.bmb.{Bmb, BmbParameter}
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import spinal.lib.bus.bmb.{Bmb, BmbCmd, BmbParameter}
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import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
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import spinal.lib.bus.simple._
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import vexriscv.plugin.DBusSimpleBus
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@ -29,7 +29,8 @@ case class DataCacheConfig(cacheSize : Int,
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withInvalidate : Boolean = false,
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pendingMax : Int = 32,
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directTlbHit : Boolean = false,
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mergeExecuteMemory : Boolean = false){
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mergeExecuteMemory : Boolean = false,
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aggregationWidth : Int = 0){
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assert(!(mergeExecuteMemory && (earlyDataMux || earlyWaysHits)))
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assert(!(earlyDataMux && !earlyWaysHits))
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assert(isPow2(pendingMax))
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@ -41,6 +42,8 @@ case class DataCacheConfig(cacheSize : Int,
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def withInternalLrSc = withLrSc && !withExclusive
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def withExternalLrSc = withLrSc && withExclusive
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def withExternalAmo = withAmo && withExclusive
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def cpuDataBytes = cpuDataWidth/8
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def memDataBytes = memDataWidth/8
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def getAxi4SharedConfig() = Axi4Config(
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addressWidth = addressWidth,
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dataWidth = memDataWidth,
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@ -79,10 +82,10 @@ case class DataCacheConfig(cacheSize : Int,
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def getBmbParameter() = BmbParameter(
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addressWidth = 32,
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dataWidth = 32,
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dataWidth = memDataWidth,
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lengthWidth = log2Up(this.bytePerLine),
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sourceWidth = 0,
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contextWidth = if(!withWriteResponse) 1 else 0,
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contextWidth = (if(!withWriteResponse) 1 else 0) + (if(cpuDataWidth != memDataWidth) log2Up(memDataBytes) else 0),
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canRead = true,
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canWrite = true,
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alignment = BmbParameter.BurstAlignement.LENGTH,
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@ -203,6 +206,7 @@ case class DataCacheMemCmd(p : DataCacheConfig) extends Bundle{
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val last = Bool
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}
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case class DataCacheMemRsp(p : DataCacheConfig) extends Bundle{
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val aggregated = UInt(p.aggregationWidth bits)
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val last = Bool()
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val data = Bits(p.memDataWidth bit)
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val error = Bool
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@ -217,7 +221,7 @@ case class DataCacheAck(p : DataCacheConfig) extends Bundle{
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}
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case class DataCacheSync(p : DataCacheConfig) extends Bundle{
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val aggregated = UInt(p.aggregationWidth bits)
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}
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case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave{
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@ -369,21 +373,133 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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}
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def toBmb() : Bmb = {
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def toBmb(syncPendingMax : Int = 16,
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timeoutCycles : Int = 16) : Bmb = new Area{
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setCompositeName(DataCacheMemBus.this, "Bridge", true)
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val pipelinedMemoryBusConfig = p.getBmbParameter()
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val bus = Bmb(pipelinedMemoryBusConfig).setCompositeName(this,"toBmb", true)
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val aggregationMax = p.memDataBytes
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bus.cmd.valid := cmd.valid
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bus.cmd.last := cmd.last
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if(!p.withWriteResponse) bus.cmd.context(0) := cmd.wr
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bus.cmd.opcode := (cmd.wr ? B(Bmb.Cmd.Opcode.WRITE) | B(Bmb.Cmd.Opcode.READ))
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bus.cmd.address := cmd.address.resized
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bus.cmd.data := cmd.data
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bus.cmd.length := (cmd.length << 2) | 3 //TODO better sub word access
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bus.cmd.mask := cmd.mask
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if(p.withExclusive) bus.cmd.exclusive := cmd.exclusive
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case class Context() extends Bundle{
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val isWrite = !p.withWriteResponse generate Bool()
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val rspCount = (p.cpuDataWidth != p.memDataWidth) generate UInt(log2Up(aggregationMax) bits)
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}
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val withoutWriteBuffer = if(p.cpuDataWidth == p.memDataWidth) new Area {
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val busCmdContext = Context()
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bus.cmd.valid := cmd.valid
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bus.cmd.last := cmd.last
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bus.cmd.opcode := (cmd.wr ? B(Bmb.Cmd.Opcode.WRITE) | B(Bmb.Cmd.Opcode.READ))
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bus.cmd.address := cmd.address.resized
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bus.cmd.data := cmd.data
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bus.cmd.length := (cmd.length << 2) | 3
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bus.cmd.mask := cmd.mask
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if (p.withExclusive) bus.cmd.exclusive := cmd.exclusive
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if (!p.withWriteResponse) busCmdContext.isWrite := cmd.wr
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bus.cmd.context := B(busCmdContext)
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cmd.ready := bus.cmd.ready
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if(p.withInvalidate) sync.arbitrationFrom(bus.sync)
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}
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val withWriteBuffer = if(p.cpuDataWidth != p.memDataWidth) new Area {
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val buffer = new Area {
|
||||
val stream = cmd.toEvent().m2sPipe()
|
||||
val address = Reg(UInt(p.addressWidth bits))
|
||||
val length = Reg(UInt(pipelinedMemoryBusConfig.lengthWidth bits))
|
||||
val write = Reg(Bool)
|
||||
val exclusive = Reg(Bool)
|
||||
val data = Reg(Bits(p.memDataWidth bits))
|
||||
val mask = Reg(Bits(p.memDataWidth/8 bits)) init(0)
|
||||
}
|
||||
|
||||
val aggregationRange = log2Up(p.memDataWidth/8)-1 downto log2Up(p.cpuDataWidth/8)
|
||||
val tagRange = p.addressWidth-1 downto aggregationRange.high+1
|
||||
val aggregationEnabled = Reg(Bool)
|
||||
val aggregationCounter = Reg(UInt(log2Up(aggregationMax) bits)) init(0)
|
||||
val aggregationCounterFull = aggregationCounter === aggregationCounter.maxValue
|
||||
val timer = Reg(UInt(log2Up(timeoutCycles)+1 bits)) init(0)
|
||||
val timerFull = timer.msb
|
||||
val hit = cmd.address(tagRange) === buffer.address(tagRange)
|
||||
val canAggregate = cmd.valid && cmd.wr && !cmd.uncached && !cmd.exclusive && !timerFull && !aggregationCounterFull && (!buffer.stream.valid || aggregationEnabled && hit)
|
||||
val doFlush = cmd.valid && !canAggregate || timerFull || aggregationCounterFull || !aggregationEnabled
|
||||
// val canAggregate = False
|
||||
// val doFlush = True
|
||||
val busCmdContext = Context()
|
||||
val halt = False
|
||||
|
||||
when(cmd.fire){
|
||||
aggregationCounter := aggregationCounter + 1
|
||||
}
|
||||
when(buffer.stream.valid && !timerFull){
|
||||
timer := timer + 1
|
||||
}
|
||||
when(bus.cmd.fire || !buffer.stream.valid){
|
||||
buffer.mask := 0
|
||||
aggregationCounter := 0
|
||||
timer := 0
|
||||
}
|
||||
|
||||
buffer.stream.ready := (bus.cmd.ready && doFlush || canAggregate) && !halt
|
||||
bus.cmd.valid := buffer.stream.valid && doFlush && !halt
|
||||
bus.cmd.last := True
|
||||
bus.cmd.opcode := (buffer.write ? B(Bmb.Cmd.Opcode.WRITE) | B(Bmb.Cmd.Opcode.READ))
|
||||
bus.cmd.address := buffer.address
|
||||
bus.cmd.length := buffer.length
|
||||
bus.cmd.data := buffer.data
|
||||
bus.cmd.mask := buffer.mask
|
||||
|
||||
if (p.withExclusive) bus.cmd.exclusive := buffer.exclusive
|
||||
bus.cmd.context.removeAssignments() := B(busCmdContext)
|
||||
if (!p.withWriteResponse) busCmdContext.isWrite := bus.cmd.isWrite
|
||||
busCmdContext.rspCount := aggregationCounter
|
||||
|
||||
val aggregationSel = cmd.address(aggregationRange)
|
||||
when(cmd.fire){
|
||||
val dIn = cmd.data.subdivideIn(8 bits)
|
||||
val dReg = buffer.data.subdivideIn(8 bits)
|
||||
for(byteId <- 0 until p.memDataBytes){
|
||||
when(aggregationSel === byteId / p.cpuDataBytes && cmd.mask(byteId % p.cpuDataBytes)){
|
||||
dReg.write(byteId, dIn(byteId % p.cpuDataBytes))
|
||||
buffer.mask(byteId) := True
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
when(cmd.fire){
|
||||
buffer.write := cmd.wr
|
||||
buffer.address := cmd.address.resized
|
||||
buffer.length := (cmd.length << 2) | 3
|
||||
if (p.withExclusive) buffer.exclusive := cmd.exclusive
|
||||
|
||||
when(cmd.wr && !cmd.uncached && !cmd.exclusive){
|
||||
aggregationEnabled := True
|
||||
buffer.address(aggregationRange.high downto 0) := 0
|
||||
buffer.length := p.memDataBytes-1
|
||||
} otherwise {
|
||||
aggregationEnabled := False
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
val rspCtx = bus.rsp.context.as(Context())
|
||||
rsp.aggregated := rspCtx.rspCount
|
||||
|
||||
val syncLogic = p.withInvalidate generate new Area{
|
||||
val cmdCtx = Stream(UInt(log2Up(aggregationMax) bits))
|
||||
cmdCtx.valid := bus.cmd.fire && bus.cmd.isWrite
|
||||
cmdCtx.payload := aggregationCounter
|
||||
halt setWhen(!cmdCtx.ready)
|
||||
|
||||
val syncCtx = cmdCtx.queueLowLatency(syncPendingMax, latency = 1)
|
||||
syncCtx.ready := bus.sync.fire
|
||||
|
||||
sync.arbitrationFrom(bus.sync)
|
||||
sync.aggregated := syncCtx.payload
|
||||
}
|
||||
}
|
||||
|
||||
cmd.ready := bus.cmd.ready
|
||||
|
||||
rsp.valid := bus.rsp.valid
|
||||
if(!p.withWriteResponse) rsp.valid clearWhen(bus.rsp.context(0))
|
||||
|
|
@ -399,21 +515,9 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
|
|||
inv.enable := bus.inv.all
|
||||
|
||||
bus.ack.arbitrationFrom(ack)
|
||||
|
||||
sync.arbitrationFrom(bus.sync)
|
||||
|
||||
// bus.ack.arbitrationFrom(ack)
|
||||
// //TODO manage lenght ?
|
||||
// inv.address := bus.inv.address
|
||||
//// inv.opcode := bus.inv.opcode
|
||||
// ???
|
||||
//
|
||||
// bus.ack.arbitrationFrom(ack)
|
||||
// //TODO manage lenght ?
|
||||
}
|
||||
|
||||
|
||||
bus
|
||||
}
|
||||
}.bus
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -537,7 +641,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
|
|||
val memCmdSent = RegInit(False) setWhen (io.mem.cmd.ready) clearWhen (!io.cpu.writeBack.isStuck)
|
||||
val pending = withExclusive generate new Area{
|
||||
val counter = Reg(UInt(log2Up(pendingMax) + 1 bits)) init(0)
|
||||
val counterNext = counter + U(io.mem.cmd.fire && io.mem.cmd.last) - U(io.mem.rsp.valid && io.mem.rsp.last)
|
||||
val counterNext = counter + U(io.mem.cmd.fire && io.mem.cmd.last) - ((io.mem.rsp.valid && io.mem.rsp.last) ? (io.mem.rsp.aggregated +^ 1) | 0)
|
||||
counter := counterNext
|
||||
|
||||
val done = RegNext(counterNext === 0)
|
||||
|
|
@ -554,7 +658,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
|
|||
|
||||
val sync = withInvalidate generate new Area{
|
||||
io.mem.sync.ready := True
|
||||
|
||||
val syncCount = io.mem.sync.aggregated +^ 1
|
||||
val syncContext = new Area{
|
||||
val history = Mem(Bool, pendingMax)
|
||||
val wPtr, rPtr = Reg(UInt(log2Up(pendingMax)+1 bits)) init(0)
|
||||
|
|
@ -564,7 +668,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
|
|||
}
|
||||
|
||||
when(io.mem.sync.fire){
|
||||
rPtr := rPtr + 1
|
||||
rPtr := rPtr + syncCount
|
||||
}
|
||||
val uncached = history.readAsync(rPtr.resized)
|
||||
val full = RegNext(wPtr - rPtr >= pendingMax-1)
|
||||
|
|
@ -573,7 +677,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
|
|||
|
||||
def pending(inc : Bool, dec : Bool) = new Area {
|
||||
val pendingSync = Reg(UInt(log2Up(pendingMax) + 1 bits)) init(0)
|
||||
val pendingSyncNext = pendingSync + U(io.mem.cmd.fire && io.mem.cmd.wr && inc) - U(io.mem.sync.fire && dec)
|
||||
val pendingSyncNext = pendingSync + U(io.mem.cmd.fire && io.mem.cmd.wr && inc) - ((io.mem.sync.fire && dec) ? syncCount | 0)
|
||||
pendingSync := pendingSyncNext
|
||||
}
|
||||
|
||||
|
|
@ -582,7 +686,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
|
|||
|
||||
def track(load : Bool, uncached : Boolean) = new Area {
|
||||
val counter = Reg(UInt(log2Up(pendingMax) + 1 bits)) init(0)
|
||||
counter := counter - U(io.mem.sync.fire && counter =/= 0 && (if(uncached) syncContext.uncached else !syncContext.uncached))
|
||||
counter := counter - ((io.mem.sync.fire && counter =/= 0 && (if(uncached) syncContext.uncached else !syncContext.uncached)) ? syncCount | 0)
|
||||
when(load){ counter := (if(uncached) writeUncached.pendingSyncNext else writeCached.pendingSyncNext) }
|
||||
|
||||
val busy = counter =/= 0
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ case class CsrPluginConfig(
|
|||
marchid : BigInt,
|
||||
mimpid : BigInt,
|
||||
mhartid : BigInt,
|
||||
misaExtensionsInit : Int,
|
||||
misaExtensionsInit : Int,
|
||||
misaAccess : CsrAccess,
|
||||
mtvecAccess : CsrAccess,
|
||||
mtvecInit : BigInt,
|
||||
|
|
@ -68,6 +68,8 @@ case class CsrPluginConfig(
|
|||
satpAccess : CsrAccess = CsrAccess.NONE,
|
||||
medelegAccess : CsrAccess = CsrAccess.NONE,
|
||||
midelegAccess : CsrAccess = CsrAccess.NONE,
|
||||
withExternalMhartid : Boolean = false,
|
||||
mhartidWidth : Int = 0,
|
||||
pipelineCsrRead : Boolean = false,
|
||||
pipelinedInterrupt : Boolean = true,
|
||||
csrOhDecoder : Boolean = true,
|
||||
|
|
@ -85,12 +87,12 @@ object CsrPluginConfig{
|
|||
def small : CsrPluginConfig = small(0x00000020l)
|
||||
def smallest : CsrPluginConfig = smallest(0x00000020l)
|
||||
|
||||
def openSbi(hartId : Int, misa : Int) = CsrPluginConfig(
|
||||
def openSbi(misa : Int) = CsrPluginConfig(
|
||||
catchIllegalAccess = true,
|
||||
mvendorid = 0,
|
||||
marchid = 0,
|
||||
mimpid = 0,
|
||||
mhartid = hartId,
|
||||
mhartid = 0,
|
||||
misaExtensionsInit = misa,
|
||||
misaAccess = CsrAccess.READ_ONLY,
|
||||
mtvecAccess = CsrAccess.READ_WRITE, //Could have been WRITE_ONLY :(
|
||||
|
|
@ -387,6 +389,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
|
|||
var contextSwitching : Bool = null
|
||||
var thirdPartyWake : Bool = null
|
||||
var inWfi : Bool = null
|
||||
var externalMhartId : UInt = null
|
||||
|
||||
override def askWake(): Unit = thirdPartyWake := True
|
||||
|
||||
|
|
@ -515,6 +518,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
|
|||
|
||||
|
||||
pipeline.update(MPP, UInt(2 bits))
|
||||
|
||||
if(withExternalMhartid) externalMhartId = in UInt(mhartidWidth bits)
|
||||
}
|
||||
|
||||
def inhibateInterrupts() : Unit = allowInterrupts := False
|
||||
|
|
@ -600,7 +605,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
|
|||
if(mvendorid != null) READ_ONLY(CSR.MVENDORID, U(mvendorid))
|
||||
if(marchid != null) READ_ONLY(CSR.MARCHID , U(marchid ))
|
||||
if(mimpid != null) READ_ONLY(CSR.MIMPID , U(mimpid ))
|
||||
if(mhartid != null) READ_ONLY(CSR.MHARTID , U(mhartid ))
|
||||
if(mhartid != null && !withExternalMhartid) READ_ONLY(CSR.MHARTID , U(mhartid ))
|
||||
if(withExternalMhartid) READ_ONLY(CSR.MHARTID , externalMhartId)
|
||||
misaAccess(CSR.MISA, xlen-2 -> misa.base , 0 -> misa.extensions)
|
||||
|
||||
//Machine CSR
|
||||
|
|
|
|||
|
|
@ -195,6 +195,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
|
|||
rsp.exclusive := RegNext(dBus.rsp.exclusive)
|
||||
rsp.error := RegNext(dBus.rsp.error)
|
||||
rsp.last := RegNext(dBus.rsp.last)
|
||||
rsp.aggregated := RegNext(dBus.rsp.aggregated)
|
||||
rsp.data := RegNextWhen(dBus.rsp.data, dBus.rsp.valid && !cache.io.cpu.writeBack.keepMemRspData)
|
||||
rsp
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue