mirror of
https://github.com/SpinalHDL/VexRiscv.git
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Add wishbone support for i$ / d$ (not tested)
This commit is contained in:
Dolu1990
parent
bd4d1eeb01
commit
a66efcb35b
3 changed files with 347 additions and 4 deletions
241
src/main/scala/spinal/lib/bus/wishbone/Wishbone.scala
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241
src/main/scala/spinal/lib/bus/wishbone/Wishbone.scala
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@ -0,0 +1,241 @@
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package spinal.lib.bus.wishbone
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import spinal.core._
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import spinal.lib._
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/** This class is used for configuring the Wishbone class
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* @param addressWidth size in bits of the address line
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* @param dataWidth size in bits of the data line
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* @param selWidth size in bits of the selection line, deafult to 0 (disabled)
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* @param useSTALL activate the stall line, default to false (disabled)
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* @param useLOCK activate the lock line, default to false (disabled)
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* @param useERR activate the error line, default to false (disabled)
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* @param useRTY activate the retry line, default to false (disabled)
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* @param tgaWidth size in bits of the tag address linie, deafult to 0 (disabled)
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* @param tgcWidth size in bits of the tag cycle line, deafult to 0 (disabled)
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* @param tgdWidth size in bits of the tag data line, deafult to 0 (disabled)
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* @param useBTE activate the BTE line, deafult to 0 (disabled)
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* @param useCTI activate the CTI line, deafult to 0 (disabled)
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* @example {{{
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* val wishboneBusConf = new WishboneConfig(32,8).withCycleTag(8).withDataTag(8)
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* val wishboneBus = new Wishbone(wishboneBusConf)
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* }}}
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* @todo test example
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*/
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case class WishboneConfig(
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val addressWidth : Int,
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val dataWidth : Int,
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val selWidth : Int = 0,
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val useSTALL : Boolean = false,
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val useLOCK : Boolean = false,
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val useERR : Boolean = false,
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val useRTY : Boolean = false,
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val tgaWidth : Int = 0,
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val tgcWidth : Int = 0,
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val tgdWidth : Int = 0,
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val useBTE : Boolean = false,
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val useCTI : Boolean = false
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){
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def useTGA = tgaWidth > 0
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def useTGC = tgcWidth > 0
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def useTGD = tgdWidth > 0
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def useSEL = selWidth > 0
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def isPipelined = useSTALL
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def pipelined : WishboneConfig = this.copy(useSTALL = true)
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def withDataTag(size : Int) : WishboneConfig = this.copy(tgdWidth = size)
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def withAddressTag(size : Int) : WishboneConfig = this.copy(tgaWidth = size)
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def withCycleTag(size : Int) : WishboneConfig = this.copy(tgdWidth = size)
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}
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/** This class rappresent a Wishbone bus
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* @param config an istance of WishboneConfig, it will be used to configurate the Wishbone Bus
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*/
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case class Wishbone(config: WishboneConfig) extends Bundle with IMasterSlave {
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/////////////////////
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// MINIMAL SIGNALS //
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/////////////////////
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val CYC = Bool
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val STB = Bool
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val ACK = Bool
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val WE = Bool
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val ADR = UInt(config.addressWidth bits)
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val DAT_MISO = Bits(config.dataWidth bits)
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val DAT_MOSI = Bits(config.dataWidth bits)
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///////////////////////////
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// OPTIONAL FLOW CONTROS //
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///////////////////////////
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val SEL = if(config.useSEL) Bits(config.selWidth bits) else null
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val STALL = if(config.useSTALL) Bool else null
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val LOCK = if(config.useLOCK) Bool else null
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val ERR = if(config.useERR) Bool else null
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val RTY = if(config.useRTY) Bool else null
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//////////
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// TAGS //
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//////////
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val TGD_MISO = if(config.useTGD) Bits(config.tgdWidth bits) else null
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val TGD_MOSI = if(config.useTGD) Bits(config.tgdWidth bits) else null
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val TGA = if(config.useTGA) Bits(config.tgaWidth bits) else null
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val TGC = if(config.useTGC) Bits(config.tgcWidth bits) else null
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val BTE = if(config.useBTE) Bits(2 bits) else null
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val CTI = if(config.useCTI) Bits(3 bits) else null
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override def asMaster(): Unit = {
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outWithNull(DAT_MOSI, TGD_MOSI, ADR, CYC, LOCK, SEL, STB, TGA, TGC, WE, CTI, BTE)
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inWithNull(DAT_MISO, TGD_MISO, ACK, STALL, ERR, RTY)
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}
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// def isCycle : Bool = if(config.useERR) !ERR && CYC else CYC
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// def isWrite : Bool = isCycle && WE
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// def isRead : Bool = isCycle && !WE
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// def isReadCycle : Bool = isRead && STB
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// def isWriteCycle : Bool = isWrite && STB
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// def isStalled : Bool = if(config.isPipelined) isCycle && STALL else False
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// def isAcknoledge : Bool = isCycle && ACK
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// def isStrobe : Bool = isCycle && STB
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// def doSlaveWrite : Bool = this.CYC && this.STB && this.WE
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// def doSlaveRead : Bool = this.CYC && this.STB && !this.WE
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// def doSlavePipelinedWrite : Bool = this.CYC && this.WE
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// def doSlavePipelinedRead : Bool = this.CYC && !this.WE
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/** Connect the istance of this bus with another, allowing for resize of data
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* @param that the wishbone instance that will be connected and resized
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* @param allowDataResize allow to resize "that" data lines, default to false (disable)
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* @param allowAddressResize allow to resize "that" address lines, default to false (disable)
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* @param allowTagResize allow to resize "that" tag lines, default to false (disable)
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*/
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def connectTo(that : Wishbone, allowDataResize : Boolean = false, allowAddressResize : Boolean = false, allowTagResize : Boolean = false) : Unit = {
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this.CYC <> that.CYC
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this.STB <> that.STB
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this.WE <> that.WE
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this.ACK <> that.ACK
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if(allowDataResize){
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this.DAT_MISO.resized <> that.DAT_MISO
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this.DAT_MOSI <> that.DAT_MOSI.resized
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} else {
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this.DAT_MOSI <> that.DAT_MOSI
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this.DAT_MISO <> that.DAT_MISO
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}
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if(allowAddressResize){
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this.ADR <> that.ADR.resized
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} else {
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this.ADR <> that.ADR
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}
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///////////////////////////
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// OPTIONAL FLOW CONTROS //
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///////////////////////////
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if(this.config.useSTALL && that.config.useSTALL) this.STALL <> that.STALL
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if(this.config.useERR && that.config.useERR) this.ERR <> that.ERR
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if(this.config.useRTY && that.config.useRTY) this.RTY <> that.RTY
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if(this.config.useSEL && that.config.useSEL) this.SEL <> that.SEL
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if(this.config.useCTI && that.config.useCTI) this.CTI <> that.CTI
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//////////
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// TAGS //
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//////////
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if(this.config.useTGA && that.config.useTGA)
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if(allowTagResize) this.TGA <> that.TGA.resized else this.TGA <> that.TGA
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if(this.config.useTGC && that.config.useTGC)
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if(allowTagResize) this.TGC <> that.TGC.resized else this.TGC <> that.TGC
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if(this.config.useBTE && that.config.useBTE)
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if(allowTagResize) this.BTE <> that.BTE.resized else this.BTE <> that.BTE
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if(this.config.useTGD && that.config.useTGD){
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if(allowTagResize){
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this.TGD_MISO <> that.TGD_MISO.resized
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this.TGD_MOSI <> that.TGD_MOSI.resized
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} else {
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this.TGD_MISO <> that.TGD_MISO
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this.TGD_MOSI <> that.TGD_MOSI
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}
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}
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}
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/** Connect common Wishbone signals
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* @example{{{wishbone1 <-> wishbone2}}}
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*/
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def <-> (sink : Wishbone) : Unit = {
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/////////////////////
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// MINIMAL SIGNALS //
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/////////////////////
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sink.CYC <> this.CYC
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sink.ADR <> this.ADR
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sink.DAT_MOSI <> this.DAT_MOSI
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sink.DAT_MISO <> this.DAT_MISO
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sink.STB <> this.STB
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sink.WE <> this.WE
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sink.ACK <> this.ACK
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///////////////////////////
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// OPTIONAL FLOW CONTROS //
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///////////////////////////
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if(this.config.useSTALL && sink.config.useSTALL) sink.STALL <> this.STALL
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if(this.config.useERR && sink.config.useERR) sink.ERR <> this.ERR
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if(this.config.useRTY && sink.config.useRTY) sink.RTY <> this.RTY
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if(this.config.useSEL && sink.config.useSEL) sink.SEL <> this.SEL
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//////////
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// TAGS //
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//////////
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if(this.config.useTGA && sink.config.useTGA) sink.TGA <> this.TGA
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if(this.config.useTGC && sink.config.useTGC) sink.TGC <> this.TGC
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if(this.config.useCTI && sink.config.useCTI) sink.CTI <> this.CTI
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if(this.config.useBTE && sink.config.useBTE) sink.BTE <> this.BTE
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if(this.config.useTGD && sink.config.useTGD){
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sink.TGD_MISO <> this.TGD_MISO
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sink.TGD_MOSI <> this.TGD_MOSI
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}
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}
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/** Clear all the relevant signals in the wishbone bus
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* @example{{{
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* val wishbone1 = master(Wishbone(WishboneConfig(8,8)))
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* val wishbone2 = slave(Wishbone(WishboneConfig(8,8)))
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* val wishbone2 = slave(Wishbone(WishboneConfig(8,8).withDataTag(8)))
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*
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* // this will clear only the following signals: CYC,ADR,DAT_MOSI,STB,WE
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* wishbone1.clearAll()
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* // this will clear only the following signals: DAT_MISO,ACK
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* wishbone2.clearAll()
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* // this will clear only the following signals: DAT_MISO,ACK,TGD_MISO
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* wishbone3.clearAll()
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* }}}
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*/
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def clearAll() : Unit = {
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/////////////////////
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// MINIMAl SIGLALS //
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/////////////////////
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if( isMasterInterface) this.CYC.clear()
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if( isMasterInterface) this.ADR.clearAll()
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if( isMasterInterface) this.DAT_MOSI.clearAll()
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if(!isMasterInterface) this.DAT_MISO.clearAll()
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if( isMasterInterface) this.STB.clear()
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if( isMasterInterface) this.WE.clear()
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if(!isMasterInterface) this.ACK.clear()
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///////////////////////////
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// OPTIONAL FLOW CONTROS //
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///////////////////////////
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if(this.config.useSTALL && !isMasterInterface) this.STALL.clear()
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if(this.config.useERR && !isMasterInterface) this.ERR.clear()
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if(this.config.useRTY && !isMasterInterface) this.RTY.clear()
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if(this.config.useSEL && isMasterInterface) this.SEL.clearAll()
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//////////
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// TAGS //
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//////////
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if(this.config.useTGA && isMasterInterface) this.TGA.clearAll()
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if(this.config.useTGC && isMasterInterface) this.TGC.clearAll()
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if(this.config.useCTI && isMasterInterface) this.CTI.clearAll()
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if(this.config.useBTE && isMasterInterface) this.BTE.clearAll()
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if(this.config.useTGD && !isMasterInterface) this.TGD_MISO.clearAll()
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if(this.config.useTGD && isMasterInterface) this.TGD_MOSI.clearAll()
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}
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}
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@ -3,9 +3,9 @@ package vexriscv.ip
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import vexriscv._
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba4.axi.{Axi4Shared, Axi4Config}
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import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4Shared}
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import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
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import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
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case class DataCacheConfig( cacheSize : Int,
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bytePerLine : Int,
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@ -46,6 +46,21 @@ case class DataCacheConfig( cacheSize : Int,
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useResponse = true,
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maximumPendingReadTransactions = 2
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)
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def getWishboneConfig() = WishboneConfig(
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addressWidth = 32,
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dataWidth = 32,
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selWidth = 4,
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useSTALL = false,
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useLOCK = false,
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useERR = true,
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useRTY = false,
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tgaWidth = 0,
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tgcWidth = 0,
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tgdWidth = 0,
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useBTE = true,
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useCTI = true
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)
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}
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@ -285,6 +300,50 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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mm
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}
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def toWishbone(): Wishbone = {
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val wishboneConfig = p.getWishboneConfig()
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val bus = Wishbone(wishboneConfig)
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val counter = Reg(UInt(log2Up(p.burstSize) bits))
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val cmdBridge = Stream (DataCacheMemCmd(p))
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cmdBridge.valid := cmd.valid
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cmdBridge.address := (cmd.address >> widthOf(counter) + 2) @@ counter @@ "00"
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cmdBridge.wr := cmd.wr
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cmdBridge.mask := cmd.mask
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cmdBridge.data := cmd.data
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cmdBridge.length := cmd.length
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cmdBridge.last := counter === cmd.length
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cmd.ready := cmdBridge.ready && (cmdBridge.wr || cmdBridge.last)
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when(cmdBridge.fire){
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counter := counter + 1
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when(cmdBridge.last){
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counter := 0
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}
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}
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val isBurst = cmdBridge.length =/= 0
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bus.ADR := cmdBridge.address
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bus.CTI := Mux(isBurst, cmdBridge.last ? B"111" | B"010", B"000")
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bus.BTE := "00"
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bus.SEL := cmdBridge.wr ? cmdBridge.mask | "1111"
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bus.WE := cmdBridge.wr
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bus.DAT_MOSI := cmdBridge.data
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cmdBridge.ready := bus.ACK
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when(cmdBridge.valid) {
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bus.CYC := True
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bus.STB := True
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}
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rsp.valid := RegNext(bus.WE && bus.ACK) init(False)
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rsp.data := RegNext(bus.DAT_MISO)
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rsp.error := False //TODO
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bus
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}
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}
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@ -3,8 +3,9 @@ package vexriscv.ip
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import vexriscv._
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import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba4.axi.{Axi4ReadOnly, Axi4Config}
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import spinal.lib.bus.avalon.{AvalonMMConfig, AvalonMM}
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import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4ReadOnly}
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import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
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import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
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case class InstructionCacheConfig( cacheSize : Int,
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@ -42,6 +43,20 @@ case class InstructionCacheConfig( cacheSize : Int,
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constantBurstBehavior = true
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)
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def getWishboneConfig() = WishboneConfig(
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addressWidth = 32,
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dataWidth = 32,
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selWidth = 4,
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useSTALL = false,
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useLOCK = false,
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useERR = true,
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useRTY = false,
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tgaWidth = 0,
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tgcWidth = 0,
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tgdWidth = 0,
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useBTE = true,
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useCTI = true
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)
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}
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@ -149,6 +164,34 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
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rsp.error := mm.response =/= AvalonMM.Response.OKAY
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mm
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}
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def toWishbone(): Wishbone = {
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val wishboneConfig = p.getWishboneConfig()
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val bus = Wishbone(wishboneConfig)
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val counter = Reg(UInt(log2Up(p.burstSize) bits))
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val pending = counter =/= 0
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val lastCycle = counter === counter.maxValue
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bus.ADR := (cmd.address >> widthOf(counter) + 2) @@ counter @@ "00"
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bus.CTI := lastCycle ? B"111" | B"010"
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bus.BTE := "00"
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bus.SEL := "1111"
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bus.WE := False
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bus.DAT_MOSI.assignDontCare()
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when(cmd.valid || pending){
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bus.CYC := True
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bus.STB := True
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when(bus.ACK){
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counter := counter + 1
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}
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}
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cmd.ready := !pending
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rsp.valid := RegNext(bus.ACK) init(False)
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rsp.data := RegNext(bus.DAT_MISO)
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rsp.error := False //TODO
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bus
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}
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}
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