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VexRiscv
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Rework/clean decompressor logic

This commit is contained in:
Charles Papon 2020-02-19 01:20:52 +01:00
parent a7440426fd
commit a684d5e4d1
1 changed files with 18 additions and 19 deletions
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31
src/main/scala/vexriscv/plugin/Fetcher.scala
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@ -43,7 +43,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
injectionPort = Stream(Bits(32 bits)) injectionPort = Stream(Bits(32 bits))
injectionPort injectionPort
} }
def pcRegReusedForSecondStage = allowPcRegReusedForSecondStage && prediction != DYNAMIC_TARGET def pcRegReusedForSecondStage = allowPcRegReusedForSecondStage && prediction != DYNAMIC_TARGET //TODO might not be required for DYNAMIC_TARGET
var predictionJumpInterface : Flow[UInt] = null var predictionJumpInterface : Flow[UInt] = null
override def haltIt(): Unit = fetcherHalt := True override def haltIt(): Unit = fetcherHalt := True
@ -253,32 +253,31 @@ abstract class IBusFetcherImpl(val resetVector : BigInt,
whenFalse = input.rsp.inst(31 downto 16) ## (input.pc(1) ? input.rsp.inst(31 downto 16) | input.rsp.inst(15 downto 0)) whenFalse = input.rsp.inst(31 downto 16) ## (input.pc(1) ? input.rsp.inst(31 downto 16) | input.rsp.inst(15 downto 0))
) )
val isRvc = raw(1 downto 0) =/= 3 val isRvc = raw(1 downto 0) =/= 3
val isBufferRvc = bufferData(1 downto 0) =/= 3
val decompressed = RvcDecompressor(raw(15 downto 0)) val decompressed = RvcDecompressor(raw(15 downto 0))
output.valid := (isRvc ? (bufferValid || input.valid) | (input.valid && (bufferValid || !input.pc(1)))) output.valid := bufferValid ? (isBufferRvc || input.valid) | (input.valid && (!input.pc(1) || input.rsp.inst(17 downto 16) =/= 3))
output.pc := input.pc output.pc := input.pc
output.isRvc := isRvc output.isRvc := isRvc
output.rsp.inst := isRvc ? decompressed | raw output.rsp.inst := isRvc ? decompressed | raw
input.ready := !output.valid || !(!output.ready || (isRvc && !input.pc(1) && input.rsp.inst(16, 2 bits) =/= 3) || (!isRvc && bufferValid && input.rsp.inst(16, 2 bits) =/= 3)) input.ready := output.ready && !(bufferValid && isBufferRvc)
addPrePopTask(() => {
when(!input.ready && output.fire && !flush /* && ((isRvc && !bufferValid && !input.pc(1)) || (!isRvc && bufferValid && input.rsp.inst(16, 2 bits) =/= 3))*/) {
input.pc.getDrivingReg(1) := True
}
})
bufferValid clearWhen(output.fire)
val bufferFill = False val bufferFill = False
when(input.fire){ when(output.ready && (isBufferRvc || input.valid)){
when(!(!isRvc && !input.pc(1) && !bufferValid) && !(isRvc && input.pc(1) && output.ready)) {
bufferValid := True
bufferFill := True
} otherwise {
bufferValid := False bufferValid := False
} }
when(output.ready && input.valid){
bufferData := input.rsp.inst(31 downto 16) bufferData := input.rsp.inst(31 downto 16)
when((!bufferValid && !input.pc(1) && input.rsp.inst(1 downto 0) =/= 3) || (bufferValid && !isBufferRvc) || (input.pc(1) && input.rsp.inst(17 downto 16) === 3)){
bufferFill := True
bufferValid := True
} }
}
bufferValid.clearWhen(flush) bufferValid.clearWhen(flush)
iBusRsp.readyForError.clearWhen(bufferValid && isRvc) //Can't emit error, as there is a earlier instruction pending when(bufferValid && isBufferRvc){
incomingInstruction setWhen(bufferValid && bufferData(1 downto 0) =/= 3) iBusRsp.readyForError := False
incomingInstruction := True
}
}) })